Zobrazeno 1 - 10
of 32
pro vyhledávání: '"C. Brunet Manquat"'
Autor:
Myriam Assous, Stephane Moreau, Jean Charbonnier, Jörg Siegert, Maxime Argoud, N. David, C. Hartler, Nacima Allouti, Ewald Wachmann, A. Plihon, C. Brunet-Manquat
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
As electronic power systems follow the general trend of miniaturization and functional density [1], this study targets reliable and low cost 3D heterogeneous integration technology using Through Silicon Vias (TSV) and Wafer Level Packaging (WLP) for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20d4d6db4b17f9e310ced5328dfe34dc
https://doi.org/10.1109/eptc.2017.8277576
https://doi.org/10.1109/eptc.2017.8277576
Autor:
O. Le-Briz, R. Franiatte, R. Prieto, Perceval Coudrain, C. Brunet-Manquat, Jean-Philippe Colonna, Y. Hallez, C. Chancel, V. Rat, Didier Campos
Publikováno v:
2017 23rd International Workshop on Thermal Investigations of ICs and Systems (THERMINIC).
Thermal dissipation is a major concern in microelectronics, especially for compact packages and 3D circuits where the dense stacking of thin silicon layers leads to a significant increase of heat densities. Direct hybrid bonding is considered as one
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0335869bfd657d3bde92bd42032b318c
https://doi.org/10.1109/therminic.2017.8233830
https://doi.org/10.1109/therminic.2017.8233830
Autor:
Myriam Assous, C. Brunet Manquat, T. Hilt, A. Plihon, C. Hartler, Thierry Mourier, H. Gruber, Jennifer Guillaume, Jean Charbonnier, J. P. Bally, Franz Schrank, A. Hassaine, R. Franiatte, K. Pressel, Jörg Siegert
Publikováno v:
2016 6th Electronic System-Integration Technology Conference (ESTC).
Electronic power systems follow the general trend of miniaturization and functional density. 3D technologies provide an interesting response if adapted to power specifications. In the framework of the ENIAC JU funded project Enhanced Power Pilot Line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04e305b3f1bb1fc63f086ccda68b759f
https://doi.org/10.1109/estc.2016.7764678
https://doi.org/10.1109/estc.2016.7764678
Autor:
P. Chausse, C. Brunet-Manquat, Christophe Aumont, A. Jouve, P. Coudrain, Severine Cheramy, Roselyne Segaud, J. P. Colonna, N. Sillon, N. Hotellier, G. Garnier, C. Laviron
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2012:000377-000397
3D integration so far has often been investigated through a face to face point of view: the top die FEOL is in front of bottom die FEOL. This allows a dense connectivity between both dies, but TSV are mandatory on the bottom die for each external exc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f08b82af02026201407ce1c6fa28b26
https://doi.org/10.4071/2012dpc-ta13
https://doi.org/10.4071/2012dpc-ta13
Conference
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Autor:
J. Pruvost, Christophe Aumont, L. Gabette, G. Garnier, A. Jouve, K. Vial, R. Segaud, Perceval Coudrain, Pascal Besson, C. Brunet-Manquat, T. Mourier, T. Magis, C. Laviron, E. Saugier, J.-P. Colonna, Severine Cheramy, Nacima Allouti, P. Chausse, Alexis Farcy, N. Hotellier
Publikováno v:
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be present
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7d44799115f0efe89935f9a8f8e382d
https://doi.org/10.1109/eptc.2012.6507102
https://doi.org/10.1109/eptc.2012.6507102
Autor:
Severine Cheramy, J. Charbonnier, C. Fuchs, Alexis Farcy, G. Garnier, C. Brunet-Manquat, J. Diaz, O. Hajji, R. Anciant, Pascal Ancey, D. Henry, P. Vincent, Lionel Cadix, N. Sillon, P. Chausse
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
In this paper, high density TSV integration in silicon interposer is presented, fully characterized and simulated (DC and RF). Parasitic elements of the RF model are extracted. Dielectric and metal process improvements are developed and their impact
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ccea25076976a54b48f9abf04661d22
https://doi.org/10.1109/iitc.2011.5940301
https://doi.org/10.1109/iitc.2011.5940301
Autor:
Alexis Farcy, R. Hida, Paul-Henri Haumesser, N. Sillon, E. Saugier, Jean Charbonnier, M. Neyret, David Henry, R. Anciant, G. Garnier, S. Cheramy, C. Brunet-Manquat, Maxime Rousseau, G. Druais, O. Hajji, Laurent Vandroux, J. Cuzzocrea, P. Chausse
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
As 3D packaging technologies are becoming more and more present in packaging roadmap, applications with higher requirement are rising continuously. Today, one of the main applications requiring 3D technologies is dedicated to nomadic components, incl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24dc21817bb7c28e8e8b7ef1ca805ca5
https://doi.org/10.1109/ectc.2010.5490835
https://doi.org/10.1109/ectc.2010.5490835
Autor:
Jean Charbonnier, N. Sillon, Sophie Verrun, E. Saugier, M. Neyret, David Henry, L. Bonnot, Severine Cheramy, C. Brunet-Manquat, G. Garnier, Alexis Farcy, Maxime Rousseau, P. Chausse, Lionel Cadix
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
Today, a new trend in wafer level packaging is to add more than one die in the same package and, sometimes, to use the third dimension in order to : • Decrease the form factor of the final system • Improve the thermal and electrical performances
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::803bc0ea31ca2bebe227eba02b716fc8
https://doi.org/10.1109/eptc.2009.5416490
https://doi.org/10.1109/eptc.2009.5416490
Autor:
M. Neyret, D. Henry, Sophie Verrun, E. Saugier, X. Gagnard, J. Charbonnier, N. Sillon, S. Cheramy, L. Bonnot, C. Brunet-Manquat, P. Chausse
Publikováno v:
3DIC
In this paper, the technological bricks specifically developed for 3D integration of a set top box demonstrator will be presented. The integration flow was based on the 45 nm technology top chip stacked on a 130 nm technology active bottom wafer [1].
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::696ea27387bf9e82b71c8df425afa0e0
https://doi.org/10.1109/3dic.2009.5306561
https://doi.org/10.1109/3dic.2009.5306561