Zobrazeno 1 - 10
of 17
pro vyhledávání: '"C S, Selvanayagam"'
Autor:
Rao Tummala, Xiaowu Zhang, Dim-Lee Kwong, Ranjan Rajoo, N. Khan, V. Kripesh, Aditya Kumar, Vempati Srinivasa Rao, Venky Sundaram, John H. Lau, C. S. Selvanayagam
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:935-943
Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b4258131c721fe50e5c666d8ca2a668
https://doi.org/10.1109/tcpmt.2012.2192731
https://doi.org/10.1109/tcpmt.2012.2192731
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:1328-1335
With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4a49054322a3d99be90222111b48c01
https://doi.org/10.1109/tcpmt.2011.2158002
https://doi.org/10.1109/tcpmt.2011.2158002
Autor:
Pinjala Damaruganath, M Ravi, John H. Lau, Ebin Liao, Vempati Srinivasa Rao, Nagarajan Ranganathan, Hong Yu Li, Yen Yi Germaine Hoe, Jiangyan Sun, Xiaowu Zhang, Eva Wai, Tai Chong Chai, C. J. Vath, C. S. Selvanayagam, Y Tsutsumi, Yue Ying Ong, Shiguo Liu, Kripesh Vaidyanathan
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:660-672
The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19099bdcb6f56725b6fe9bc40b06a81b
https://doi.org/10.1109/tcpmt.2010.2101911
https://doi.org/10.1109/tcpmt.2010.2101911
Autor:
C. S. Premachandran, Dim-Lee Kwong, Xiaowu Zhang, S. Gao, Siong Chiew Ong, Won Kyoung Choi, Yee Mong Khoo, Ranjan Rajoo, Ling Xie, Damaruganath Pinjala, Soon Wee Ho, C. S. Selvanayagam
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:510-518
Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints, comprise
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc3758a8ee9cd5673dca2480b9cf848f
https://doi.org/10.1109/tcpmt.2011.2107511
https://doi.org/10.1109/tcpmt.2011.2107511
Autor:
X.J. Zhao, C. S. Selvanayagam, P.L. Eu, J.F.J.M. Caers, Yi-Shao Lai, L.C. Tan, W.D. van Driel, Ranjan Rajoo, S.K.W. Seah, M. Leoni, N. Owens, C.-L. Yeh, Ee Hua Wong
Publikováno v:
Microelectronics Reliability. 48:1069-1078
This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop-impact on a portable electronic product. Two test methods are used in this study: the board le
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3c0c3255db5da67da31c576bcaf5301
https://doi.org/10.1016/j.microrel.2008.04.008
https://doi.org/10.1016/j.microrel.2008.04.008
Publikováno v:
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
In wirebonding, high stresses applied onto the pad during the ultrasonic bonding can result in pad damage, silicon cratering and aluminium splash — all of which ultimately result in poor joint quality. Cracking in the Cu/low-k and Cu/ultra low-k la
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e830ecdd91fb6aa1a01a5f4b80654746
https://doi.org/10.1109/eptc.2012.6507086
https://doi.org/10.1109/eptc.2012.6507086
Autor:
Ranjan Rajoo, S. Gao, Dim-Lee Kwong, Fa Xing Che, C. S. Selvanayagam, Won Kyoung Choi, Xiaowu Zhang, G. Q. Lo
Publikováno v:
3DIC
In new applications (such as MEMS, bio-MEMS), vertical integration requires a low processing temperature below 200°C to bond these devices without degrading their performance. Low temperature bonds are thin intermetallic compounds (IMCs) bonds that
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1aaf081c4f4bdcddee8cc4f50bbff683
https://doi.org/10.1109/3dic.2012.6263009
https://doi.org/10.1109/3dic.2012.6263009
Autor:
Dim-Lee Kwong, C. S. Selvanayagam, Aditya Kumar, V. Kripesh, Ranjan Rajoo, R.R. Tummula, John H. Lau, Xiaowu Zhang, Vempati Srinivasa Rao, Venky Sundaram, N. Khan
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
Though an understanding on the development of residual stresses in silicon device after chip level packaging processes has been investigated in previous studies, little is known about the development of stresses after wafer bumping process. In this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb42ce9bf7cbab5a9b6897075c5a3349
https://doi.org/10.1109/ectc.2011.5898675
https://doi.org/10.1109/ectc.2011.5898675
Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking
Autor:
Ke Wu Bai, Serene Thew, Ebin Liao, C. S. Premachandran, C. S. Selvanayagam, Ling Xie, Won Kyoung Choi, Ying Zhi Zeng, Siong Chiew Ong, V. N. Sekhar, A. Khairyanto
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
An IMC based low temperature solder
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c6ff3ccbe27aa2b0da99d1b18432f75
https://doi.org/10.1109/ectc.2011.5898526
https://doi.org/10.1109/ectc.2011.5898526
Autor:
Xiaowu Zhang, Teck Guan Lim, David Ho, Yee Mong Khoo, Gao Shan, Xiong Yong Zhong, C. S. Selvanayagam, Rui Li
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
A novel Through Silicon Via (TSV) structure to mitigate the high electrical loss at high frequency is presented here. At low frequency, the loss for the TSV is caused mainly by the material loss of the Silicon (Si) substrate due to its low resistivit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::503b341a7fb8e0fe890a30a2a8ca259a
https://doi.org/10.1109/ectc.2011.5898570
https://doi.org/10.1109/ectc.2011.5898570