Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Byung-lyul Park"'
Autor:
Byung Lyul Park, Ja Hyung Han, Young Jae Kang, Ja Eung Koo, Kyo Se Choi, Sun Yong Lee, Sang Rok Hah, Jin-Goo Park, Ju Hyuk Chung
Publikováno v:
Solid State Phenomena. 134:295-298
The prevention of watermark defect after copper/low-k CMP is a critical barrier for the successful integration of sub-100 nm devices. The water-mark can act as a leakage source and cause electrical shorts. The mechanism of water-mark formation during
Autor:
Insoo Cho, Ja Hyung Han, Seong-Il Kim, Ja Eung Koo, Byung Lyul Park, Jin-Goo Park, Ahmed Busnaina, Dae Hong Eom, Duk Ho Hong
Publikováno v:
Solid State Phenomena. :369-372
Corrosion on specific Cu patterns was evaluated during Cu CMP. The corrosion was observed at isolated patterns and outer edge area of pad surrounded by oxide field after polishing and showed dependency on process. Two different commercial slurries we
Autor:
Kwang Myeon Park, Sang Rok Hah, Chan Geun Park, Jeff Barnes, Ju Hyuk Chung, Byung Lyul Park, Uk Sun Hong, Hong Seong Son, Jun Hwan Oh
Publikováno v:
Solid State Phenomena. 92:259-262
Autor:
Moon Yong Lee, Myoung Bum Lee, Jung-min Ha, Young Bum Koh, U. In Chung, Sang-In Lee, Young Wook Park, Byung Lyul Park, Hyeon Deok Lee, Young-sun Kim, Dae Hong Ko
Publikováno v:
Journal of Electronic Materials. 26:L1-L5
We have developed tungsten nitride (W-Nitride) films grown by plasma enhanced chemical vapor deposition (PECVD) for barrier material applications in ultra large scale integration DRAM devices. As-deposited W-Nitride films show an amorphous structure,
Autor:
Yeong-lyeol Park, Ki-Young Yun, Jiwoong Sue, Kwang-jin Moon, Chilhee Chung, So-Young Lee, Jin-ho An, Gil-heyun Choi, Byung-lyul Park, Ho-Jun Lee, Ho-Kyu Kang, Do-Sun Lee
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
Stresses induced by the large volume of Cu in Through Silicon Vias (TSV) can result in global/local Cu extrusion which may affect reliability in 3D chip stacking technologies beyond the 28 nm node for high performance mobile devices. In this work, TS
Autor:
null DeokYoung Jung, null Kwang-Jin Moon, null Byung-Lyul Park, null Gilheyun Choi, null Ho-Kyu Kang, null Chilhee Chung, null Deok Young Jung, null Yonghan Rho
Publikováno v:
2012 SEMI Advanced Semiconductor Manufacturing Conference.
As semiconductor performance improvements through device scale-down becomes more difficult, 3D chip stacking technology with TSVs (Through Silicon Via) is becoming an increasingly attractive solution to achieve higher system performances by way of hi
Autor:
Byung-lyul Park, Jong Myeong Lee, Gil-heyun Choi, Hyeon-deok Lee, Zung-Sun Choi, Joo-Tae Moon
Publikováno v:
2009 IEEE International Reliability Physics Symposium.
Electromigration in a hybrid interconnect which consists of copper metallization in via below, aluminum metallization in via above, and tungsten via in between has been investigated. Fatal failures are found to occur in copper segments of the hybrid
Autor:
June Moon, G.H. Choi, Hyun-Soo Park, Ju-Wan Kim, Jang-Hee Lee, Eunjin Lee, Jong Won Hong, Zung-Sun Choi, Hye-Lan Lee, Kihyun Choi, Byung Lyul Park, JumHan Bae, H.-K. Jung
Publikováno v:
2008 International Interconnect Technology Conference.
Voltage ramp dielectric breakdown (VRBD) and time-dependent dielectric breakdown (TDDB) characteristics of ~40nm-wide Cu/SiO 2 interconnect dielectrics were investigated. The addition of a SiH 4 treatment before capping SiN deposition led to more uni
Autor:
Byung Lyul Park, Jong-min Baek, J.H. Jung, Jang-Yong Bae, G.H. Choi, G.J. Seong, H.B. Lee, Joo Tae Moon, Jang-Hee Lee, J.H. Son, Jae-joon Oh, S.Y. Lee, Sun-Rae Kim, Sang-rok Hah, Kihyun Choi, Hee-sook Park, U-In Chung, Jong Won Hong
Publikováno v:
2007 IEEE International Interconnect Technology Conferencee.
This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of