Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Byongwook Na"'
Autor:
Jeong-Don Ihm, Byongwook Na, Hye-In Choi, Kim Sang-Yun, Seung-Jun Bae, Jae-Hoon Jung, Jin-Seok Heo, Seung-Jun Lee, Dae Hyun Kim, Junghwan Park, Won-Il Bae, Ki-Han Kim, Seouk-Kyu Choi, Jin-Hun Jang, Hangi-Jung, Duk-ha Park, Jung-Bae Lee, Seungki Hong, Young-Il Lim, Isak Hwang, Dong-Hun Lee, Kyungryun Kim, Nam Sung Kim, Dae-Hyun Kwon, Chang-Kyo Lee, Dongkeon Lee, Hyung-Joon Chi, Geun-Tae Park
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:212-224
An 8.5-Gb/s/pin (Gb/s) 12-Gb LPDDR5 SDRAM is implemented in a second-generation 10-nm DRAM process with a hybrid-bank architecture that provides a power-optimized bank solution depending on the bank modes (4B/4BG, 16B-merged bank, 8B-split bank). Bas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14d89c19ed61d41454dba483b0be2a36
https://doi.org/10.1109/jssc.2020.3017775
https://doi.org/10.1109/jssc.2020.3017775
Autor:
Hyong-Ryol Hwang, Young-Soo Sohn, Young Hoon Son, Seungseob Lee, Seung-Jun Bae, Hyuck-Joon Kwon, Jung-Bae Lee, Byongwook Na, Chang-Kyo Lee, Young-Hwa Kim, Dongkeon Lee, Duk-ha Park, Daesik Moon, Kwang-Il Park, Tae-Young Oh, Youn-sik Park, Kyung-Soo Ha
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:157-166
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM is implemented in a 1 $\times$ nm DRAM process. Various techniques are applied to achieve higher bandwidth and lower power than LPDDR4X. To increase data rate, a WCK clocking scheme that is less vulnerable to power no
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3c0d249a308f28f1535a7ab42eb92fc
https://doi.org/10.1109/jssc.2019.2938396
https://doi.org/10.1109/jssc.2019.2938396
Autor:
Seouk-Kyu Choi, Young-Kwan Kim, Seung-Jun Bae, Seung-Hyun Cho, Jae-Woo Jung, Dae Hyun Kim, Byung-Cheol Kim, Sung-Woo Yoon, Jae-Koo Park, Yong-Hun Kim, Si-Hyeong Cho, Jung-Bae Lee, Jinyong Choi, Dae-Hyun Kwon, Seong-hoon Kim, Chan-Young Kim, Byongwook Na, Yong-Jun Kim, Jae-Woo Lee, Dong-Yeon Park, Hye-In Choi, Reum Oh, Hyung-Jin Kim, Min-Su Ahn, Dongkeon Lee, Jihwa You, Nam Sung Kim, Jaemin Choi, Jun-Ho Kim, Jeong-Don Ihm, Hyung-Seok Cha, Kyoung-Ho Kim, Young-Jae Park, Min-Soo Jang
Publikováno v:
ISSCC
The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa0248e1efec4151e800304c25c07a72
https://doi.org/10.1109/isscc42613.2021.9366050
https://doi.org/10.1109/isscc42613.2021.9366050
Autor:
Kim Sang-Yun, Junghwan Park, Soo-bong Chang, Won-Il Bae, Ki-Won Park, Hyuck-Joon Kwon, Seung-Jun Bae, Geun-Tae Park, Hyung-Joon Chi, Kyung-Ho Lee, Hye-In Choi, Ji-Suk Kwon, Gil-Young Kang, Seung-Jun Lee, Hyunyoon Cho, Jin-Seok Heo, Young-Soo Sohn, Lim Suk-Hyun, Kyung Ryun Kim, Kwang-Il Park, Daesik Moon, Chang-Kyo Lee, Jae-Hoon Jung, Dongkeon Lee, Chang-Ho Shin, Cheol Kim, Jung-Bae Lee, Young-Il Lim, Dae Hyun Kim, Jinsol Park, Seouk-Kyu Choi, Jin-Hun Jang, Ki-Han Kim, Young Hoon Son, Byongwook Na, Isak Hwang, Duk-ha Park, Su-Yeon Doo, Choi Yeon-Kyu
Publikováno v:
ISSCC
Energy efficiency in mobile devices is a pivotal criteria from the overall system point of view, Although the 7,5Gb/s 8Gb LPDDR5 [1], with low-power schemes (internal data copy, dynamic-voltage-frequency scaling (DVFS), and a deep-sleep mode (DSM)),
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2d3bf8b7cf0e24bdfbbca56a91c30e7
https://doi.org/10.1109/isscc19947.2020.9062914
https://doi.org/10.1109/isscc19947.2020.9062914
Autor:
Soo-bong Chang, Young-Soo Sohn, Hyuck-Joon Kwon, Duk-ha Park, Hyong-Ryol Hwang, Junghwan Park, Kwang-II Park, Choi Yeon-Kyu, Young Hoon Son, Hyunyoon Cho, Byongwook Na, Hyung-Joon Chi, Lim Suk-Hyun, Jin-Hun Jang, Tae-Young Oh, Seung-Jun Shin, Seouk-Kyu Choi, Daesik Moon, Kim Sang-Yun, Ki-Won Park, Seong-Jin Jang, Hyo-Joo Ahn, Jung-Hwan Choi, Seungseob Lee, Chang-Kyo Lee, Dongkeon Lee, Young-Hwa Kim, Youn-sik Park, Kyung-Soo Ha, Seok-Hun Hyun
Publikováno v:
ISSCC
High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1–3], have been developed to enable high-resolution displays, multiple cameras and 4G communication in mobile devices. However, DRAM with higher bandwidth and lower
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f8b77e89febd51cb1428fa3986dea1f
https://doi.org/10.1109/isscc.2019.8662509
https://doi.org/10.1109/isscc.2019.8662509
Autor:
Min-Soo Jang, Joung-Wook Moon, Young-Hyun Jun, Hyunyoon Cho, Hanna Park, Ho-Young Kim, Jong-Min Bang, Hyong-Ryol Hwang, Joo-Sun Choi, Jin-Guk Kim, Sang-Kyu Kang, Jung-Bae Lee, Ho-Cheol Lee, Sooman Hwang, Jung-Sik Kim, Donghyuk Lee, Cheolmin Han, Ki-Won Park, Byongwook Na, So-Young Kim, Kye-Hyun Kyung, Chi Sung Oh, Jang-Woo Ryu
Publikováno v:
ISSCC
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read operating power during 4 channel operation, achieving 12.8 GB/s data bandwidth. Test correlation techniques to verify fu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4a93d80e07a726da5ebd37c33ab3067
https://doi.org/10.1109/jssc.2011.2164731
https://doi.org/10.1109/jssc.2011.2164731
Autor:
Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun
Publikováno v:
2011 IEEE International Solid-State Circuits Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3038919abd2d77f23dead834dde358a
https://doi.org/10.1109/isscc.2011.5746413
https://doi.org/10.1109/isscc.2011.5746413