Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Buvna Ayyagari"'
Autor:
Fuxi Cai, She-Hwa Yen, Apurva Uppala, Luke Thomas, Tianchi Liu, Peter Fu, Xiaofeng Zhang, Ambrose Low, Deepak Kamalanathan, Joe Hsu, Buvna Ayyagari-Sangamalli
Publikováno v:
Advanced Intelligent Systems, Vol 4, Iss 8, Pp n/a-n/a (2022)
As the demands of big data applications and deep learning continue to rise, the industry is increasingly looking to artificial intelligence (AI) accelerators. Analog in‐memory computing (AiMC) with emerging nonvolatile devices enable good hardware
Externí odkaz:
https://doaj.org/article/7d38f5f69ff847f1aa7bda2e82d0e452
Autor:
Ashish Pal, Vinod Reddy, Blessy Alexander, El Mehdi Bazizi, Jongchol Kim, Buvna Ayyagari-Sangamalli, Liu Jiang
Publikováno v:
IEEE Transactions on Electron Devices. 68:5358-5363
Design technology co-optimization (DTCO) has been a workhorse in optimizing logic technology innovations for a few generations now. With increased complexity associated with each new node and the growing number of technological innovations, it is tim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::453bd3e4c0f8103e48000e614d24d473
https://doi.org/10.1109/ted.2021.3076757
https://doi.org/10.1109/ted.2021.3076757
Autor:
Sefa Dag, Liu Jiang, Prayudi Lianto, Gilbert See, Jinho An, Raghav Sreenivasan, Arvind Sundarajjan, Buvna Ayyagari-Sangamalli, El Mehdi Bazizi
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::654a98c50146ff69154b7c717b23211c
https://doi.org/10.1109/eptc56328.2022.10013200
https://doi.org/10.1109/eptc56328.2022.10013200
Autor:
Srikrishna Sitaraman, Liu Jiang, Sefa Dag, Mohammad Masoomi, Ying Wang, Prayudi Lianto, Jinho An, Ruiping Wang, Gilbert See, Arvind Sundarrajan, El Mehdi Bazizi, Buvna Ayyagari-Sangamalli
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ef087289b36d625afb32af4573ee8b5
https://doi.org/10.1109/ectc51906.2022.00116
https://doi.org/10.1109/ectc51906.2022.00116
Autor:
Pratik B. Vyas, Ashish Pal, Stephen Weeks, Joshua Holt, Aseem K. Srivastava, Ludovico Megalini, Siddarth Krishnan, Michael Chudzik, El Mehdi Bazizi, Buvna Ayyagari-Sangamalli
Publikováno v:
Solid-State Electronics. 200:108548
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f28b751caf42d257e75437de2f16387
https://doi.org/10.1016/j.sse.2022.108548
https://doi.org/10.1016/j.sse.2022.108548
Publikováno v:
2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Gate-all-around (GAA) transistor architecture offers more design flexibility in choosing a nanosheet width tailored for a given application. This is a unique advantage of GAA over FinFET, where the channel perimeter (Weff) is quantized, mostly determ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74da86fbfb29cf4830b4d69eabbcfb2c
https://doi.org/10.1109/sispad54002.2021.9592579
https://doi.org/10.1109/sispad54002.2021.9592579
Publikováno v:
2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Nanosheet on nanosheet configured complementary FET (CFET) is investigated using the Materials to Systems Co-optimization (MSCOTM) modeling framework at both device and circuit levels developed at Applied Materials. Compared to N3 FinFET with the sam
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::086d0744cd3524c64e0477028d79969b
https://doi.org/10.1109/sispad54002.2021.9592562
https://doi.org/10.1109/sispad54002.2021.9592562
Autor:
Ashish Pal, Gill Yong Lee, Bhuyan Bhaskar Jyoti, Amy Child, Gabriela Alva, David Hwang, Tomohiko Kitajima, Kang Sung-Kwan, Nancy Fung, Liu Jiang, Blessy Alexander, El Mehdi Bazizi, Chang Seok Kang, Buvna Ayyagari, Takehito Koshizawa
Publikováno v:
2021 IEEE International Memory Workshop (IMW).
We demonstrate an integration scheme for a 3D NAND memory cell with non-replacement word line (WL) by investigating the cell characteristics, including program, erase, retention, and interference based on our in-house process and device flow of 3D NA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b6afe91e56692ed3f04e5aef02dc92c
https://doi.org/10.1109/imw51353.2021.9439599
https://doi.org/10.1109/imw51353.2021.9439599
Autor:
Jaehyun Lee, El Mehdi Bazizi, Victor Moroz, Sanjay Natarajan, Xi-Wei Lin, Buvna Ayyagari-Sangmalli, Benjamin Colombeau, Ashish Pal, Blessy Alexander, Plamen Asenov
Publikováno v:
Design-Process-Technology Co-optimization XV.
In this paper, we describe a framework to enable the memory array simulations for Materials to Systems CooptimizationTM (MSCOTM) flows. The methodology is applied for projected 3 nm logic FinFET technology node SRAM array. To form the SRAM array, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d920dfe387f7501d3d9daa025e7ab2e
https://doi.org/10.1117/12.2583923
https://doi.org/10.1117/12.2583923
Publikováno v:
2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Via size and placement for layer-to-layer connection needs careful assessment. Small via size offers compact pitch and denser connections between metal layers, while larger via size offers reduced resistance for better performance. In this paper, an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c85331101f1475f124e6f6371d42766
https://doi.org/10.23919/sispad49475.2020.9241685
https://doi.org/10.23919/sispad49475.2020.9241685