Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Burst mode clock and data recovery"'
Autor:
Junichi Nakagawa, Kuniaki Motoshima, Kenichi Nakura, Seiji Kozaki, Takeshi Suehiro, Naoki Suzuki
Publikováno v:
IEICE Transactions on Communications. :987-994
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96368b5a29047f95d43ae06485b3caec
https://doi.org/10.1587/transcom.2017oap0001
https://doi.org/10.1587/transcom.2017oap0001
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:743-751
A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67c7e22674552ef7999c84a542d0e4c6
https://doi.org/10.1109/tcsi.2014.2367573
https://doi.org/10.1109/tcsi.2014.2367573
Publikováno v:
Journal of the Institute of Electronics and Information Engineers. 50:87-95
In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1e765e7aed4b4ff53b4bbc90323edbc
https://doi.org/10.5573/ieek.2013.50.7.087
https://doi.org/10.5573/ieek.2013.50.7.087
Publikováno v:
APCCAS
This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric VCO's. Compared with the conventional structure with a T/2 delay cell based approach, the proposed structure shows the better re timing margin without any d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::13b73004164a4059f7dd282a86690f7a
https://doi.org/10.1109/apccas.2016.7803971
https://doi.org/10.1109/apccas.2016.7803971
Autor:
Bhavin J. Shastri, David V. Plant
Publikováno v:
IEEE Journal of Selected Topics in Quantum Electronics. 16:1298-1320
In this paper, we demonstrate a 5/10-Gb/s burst-mode clock and data recovery circuit (BM-CDR) for passive optical network (PON) applications. The BM-CDR is based on a phase-tracking oversampling (semiblind) CDR circuit operated at twice the bit rate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0dccb9fe83c848a217d85b3a9f3a07f
https://doi.org/10.1109/jstqe.2010.2041326
https://doi.org/10.1109/jstqe.2010.2041326
Autor:
Minoru Togashi, Kazuyoshi Nishimura, Shunji Kimura, Masafumi Nogawa, Kiyomi Kumozaki, Yusuke Ohtomo, Tomoaki Yoshida, Tomoaki Kawamura
Publikováno v:
IEICE Transactions on Electronics. :903-910
A high-speed serial, 10-Gb/s, passive optical network (PON) is a good candidate for a future PON system. However, there are several issues to be solved in extending the physical speed to 10Gb/s. The issues focused on here are not only the data rate,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11400a6c3e2feb1d412072c9b009af46
https://doi.org/10.1093/ietele/e91-c.6.903
https://doi.org/10.1093/ietele/e91-c.6.903
Publikováno v:
IEICE Transactions on Communications. :1397-1402
We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by risi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::803b8c73b663a8dbdddf473a5634e774
https://doi.org/10.1093/ietcom/e91-b.5.1397
https://doi.org/10.1093/ietcom/e91-b.5.1397
Autor:
Mingchung Liu, Jri Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:619-630
A 20-Gb/s clock and data recovery circuit incorporates injection-locking technique to achieve high-speed operation with low power dissipation. The circuit creates spectral line at the frequency of data rate and injection-locks two cascaded LC oscilla
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a8b9ecdaba5e27242fc0d0b0e4bb19c2
https://doi.org/10.1109/jssc.2007.916598
https://doi.org/10.1109/jssc.2007.916598
Publikováno v:
IEICE Transactions on Electronics. :802-810
A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a07349bc8ff567e384c4b940dfab270d
https://doi.org/10.1093/ietele/e90-c.4.802
https://doi.org/10.1093/ietele/e90-c.4.802
Publikováno v:
IEICE Electronics Express. 14:20161045-20161045
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b6417ef37a081a3fb26464e422e0a48
https://doi.org/10.1587/elex.13.20161045
https://doi.org/10.1587/elex.13.20161045