Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Burak Catli"'
Autor:
Mehdi Khanpour, Shiwei Sheng, Afshin Momtaz, Delong Cui, Tim He, Ali Nazemi, Tamer Ali, Heng Zhang, Burak Catli, Ben Rhew, Yonghyun Shim, Jun Cao, Guansheng Li, Bo Zhang, Kangmin Hu, Hairong Yu
Publikováno v:
ISSCC
At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul network
Autor:
Anand Vasani, Delong Cui, Afshin Momtaz, Bharath Raghavan, Jun Cao, Zhi Chao Huang, Ullas Singh, Hassan Maarefi, Deyi Pi, Burak Catli
Publikováno v:
ISSCC
A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 pspp I
Autor:
Mona M. Hella, Burak Catli
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:1575-1589
This paper proposes the use of N-push operation for combining the functions of the VCO and divider in the mm-wave frequency range. If employed in a PLL, the combined VCO/divider (C-VCO/D) would potentially provide wider tuning range than traditional
Autor:
Mona M. Hella, Burak Catli
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2463-2477
This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates
Autor:
Ali Nazemi, Burak Catli, Zhi Huang, Afshin Momtaz, Delong Cui, Tim He, Kangmin Hu, Bo Zhang, Ullas Singh, Jun Cao
Publikováno v:
ISSCC
At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more sev
Autor:
Wei Zhang, Mahmoud Reza Ahmadi, Heng Zhang, Mohammed Abdul-Latif, Tamer Ali, Seong-Ho Lee, Guansheng Li, Afshin Momtaz, Burak Catli, Zhi Huang, Duke Tran
Publikováno v:
A-SSCC
This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2–6.8Gb/s while supporting a wide range of
Autor:
Mona M. Hella, Burak Catli
Publikováno v:
Proceedings of the 2010 ACM international workshop on mmWave communications: from circuits to networks.
A frequency synthesizer architecture is presented, which alleviates the problems in the interaction between the VCO and the divider in typical mm-wave synthesizers. The presented architecture eliminates the need for an injection locked frequency divi
Autor:
Mona M. Hella, Burak Catli
Publikováno v:
CICC
This paper proposes the use of N-push operation for combining the functions of the VCO and dividers in the mm-wave frequency range. If employed in a PLL, the combined VCO/divider (C-VCO/D) would potentially provide wider tuning range than traditional
Autor:
Mona M. Hella, Burak Catli
Publikováno v:
2009 IEEE Radio Frequency Integrated Circuits Symposium.
This paper presents a 2.1/3.9 GHz oscillator based on switching the negative resistance bandwidth of a capacitively degenerated common collector stage, while using a high order resonance tank. Multi-band oscillators have traditionally been implemente
Autor:
Mona M. Hella, Burak Catli
Publikováno v:
ISCAS
Methodologies for a manufacturable design, and layout optimization of voltage controlled oscillators in triple push architectures for mm-wave applications, are proposed. The techniques are applied in the design of a fully-monolithic 30GHz triple push