Zobrazeno 1 - 10
of 469
pro vyhledávání: '"Bubble memory"'
Autor:
Azad Naeemi, Chenyun Pan
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 3, Pp 10-17 (2017)
For the conventional spin-transfer torque random access memory, tradeoffs exist between read margin and write energy because both read and write currents pass through the same magnetic tunnel junction. To improve the read/write performance and reduce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::71a4e62aef5ceaecb3f0abe699a5370d
https://ieeexplore.ieee.org/document/7856892/
https://ieeexplore.ieee.org/document/7856892/
Autor:
Dean A. Klein
Publikováno v:
IEEE Solid-State Circuits Magazine. 8:16-22
Often taken for granted, solid-state semiconductor memory is the enabler of the contemporary digital world. Today's memory chips pack billions of transistors onto single slivers of silicon and push the boundaries of both packaging and density. In thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64ee4def3b7bd6d062e6b0e0f482f82b
https://doi.org/10.1109/mssc.2016.2548422
https://doi.org/10.1109/mssc.2016.2548422
Publikováno v:
ICDE
Around 2010, we observed significant research activity around the development of non-volatile memory technologies. Shortly thereafter, other research communities began considering the implications of non-volatile memory on system design, from storage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::10a90d9eb9a0d4159c38e08be10175d5
https://doi.org/10.1109/icde.2018.00011
https://doi.org/10.1109/icde.2018.00011
Publikováno v:
IEEE Transactions on Nanotechnology. 14:992-997
We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6a4cc760fc31d09ef21433ca8fdab57
https://doi.org/10.1109/tnano.2015.2462337
https://doi.org/10.1109/tnano.2015.2462337
Publikováno v:
IEEE Transactions on Multi-Scale Computing Systems. 1:127-137
This paper deals with a so-called racetrack memory (also commonly known as a domain-wall memory). Novel circuits for implementing the write, the read, and the shift operations of a Perpendicular Magnetic Anisotropic (PMA) based racetrack cell are ini
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8a55a7f64fd50dd3ff96824299dadce
https://doi.org/10.1109/tmscs.2015.2503282
https://doi.org/10.1109/tmscs.2015.2503282
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 15:286-291
For highly scalable NAND flash memory applications, a compact (4F2/cell) nonvolatile memory architecture is proposed and investigated via threedimensional device simulations. The back-channel program/erase is conducted independently from the front-ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d29fce7249ae224107addc4a75a7a67a
https://doi.org/10.5573/jsts.2015.15.2.286
https://doi.org/10.5573/jsts.2015.15.2.286
Autor:
Jan Van Houdt
Publikováno v:
2017 IEEE International Memory Workshop (IMW).
Recently, memory technology has chosen to continue in the 3rd dimension. This has enabled the extension of Moore's law for standalone memory, mainly in the nonvolatile area. Meanwhile, all manufacturers of high density NAND memories have made the tur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fb1ab6c97903b2601214ba113847870
https://doi.org/10.1109/imw.2017.7939066
https://doi.org/10.1109/imw.2017.7939066
Autor:
Yuval Cassuto, Evyatar Hemo
Publikováno v:
ISIT
For an array of memory cells that are read by threshold measurements, we ask the question of how to choose the measurements in the read sequence to minimize the number of measurements before the array is fully read. We propose and study analytically
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ae0d7d01273695f704150ce1bebffa9f
https://doi.org/10.1109/jsac.2014.140505
https://doi.org/10.1109/jsac.2014.140505
Autor:
G. Molas, R. Kies, A. De Luca, C. Tallaron, B. De Salvo, Christelle Charpin-Nicolle, O. Cueto, G. Médico, A. Persico, F. Aussenac, L. Masoero
Publikováno v:
Microelectronic Engineering. 118:15-19
Graphical abstractUltra-scaled self-aligned split-gate memories were fabricated with memory gate lengths of 16nm and select gate lengths of 30nm; charge trapping layer is Si3N4. Functionality of such memories was demonstrated, with a programming wind
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f37a137f395606bc7e9643bf74c44e0
https://doi.org/10.1016/j.mee.2013.12.024
https://doi.org/10.1016/j.mee.2013.12.024