Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Bruce Woolery"'
Autor:
Bruce Woolery, Abdur Rahman, J.-Y. Yeh, P. Bai, M. Jamil, K. Phoa, C.-H. Jan, Curtis Tsai, G. Curello, J. Hicks, M. S. Rahman, Joodong Park
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9fd0814444461441fe012d7275e86cfe
https://doi.org/10.1109/irps.2013.6532105
https://doi.org/10.1109/irps.2013.6532105
Autor:
Q. Zhao, C. Parker, M. Liu, S. Pae, J. Hatfield, S. Batzer, Chetan Prasad, S. Ramey, Anisur Rahman, R. Lu, J. Thomas, J. Hicks, Bruce Woolery
Publikováno v:
2012 IEEE International Reliability Physics Symposium (IRPS).
Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moore's law [1–2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB vol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fe3a697dd8dc3f96a1a1d4772d651a4
https://doi.org/10.1109/irps.2012.6241848
https://doi.org/10.1109/irps.2012.6241848
Autor:
Tahir Ghani, Richard Purser, Jingyoo Choi, Mark Y. Liu, Chris Parker, Ashwin Ashok, Jun He, Sangwoo Pae, Karen Lemay, Paul A. Packan, Bruce Woolery, Ryan Lu, Anthony St. Amour, Seok-Hee Lee
Publikováno v:
2010 IEEE International Reliability Physics Symposium.
High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction of new materials and requirement of higher field of operation for higher performance. In this paper, key and unique HK+MG intrinsic tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::52f59214a769955ea8a00bbac12330e9
https://doi.org/10.1109/irps.2010.5488814
https://doi.org/10.1109/irps.2010.5488814
Autor:
Bruce Woolery, Swaminathan Sivakumar, C. Kenyon, Ramune Nagisetty, M. Bost, Cory E. Weber, P. Bai, Jack Hwang, T. Marieb, C. Auth, Kevin Zhang, Andrew Ott, Yeoh Andrew W, Sridhar Balakrishnan, D. Ingerly, C. Parker, J. Sebastian, Ruth A. Brain, Makarem A. Hussein, J. Neirynck, Anand Portland Murthy, Z. Ma, Seung Hwan Lee, Nick Lindert, Joseph M. Steigerwald, E. Lee, Mark Y. Liu, R. Shaheed, M. Bohr, R. Heussner, J. Jeong, V. Chikarmane, Sanjay Natarajan, R. James, S. Tyagi
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac646c890427393477aae9a64374b642
https://doi.org/10.1109/iedm.2004.1419253
https://doi.org/10.1109/iedm.2004.1419253
Autor:
Jin Lee, Anne Sauter Mack, Harry Fujimoto, Linda Keys, Bruce Woolery, Qing Ma, T. Marieb, Paul A. Flinn
Publikováno v:
MRS Proceedings. 391
We have studied stress states in chemical vapor deposited (CVD) tungsten (W) for both blanket films and lines, to understand better the mechanical implications of intrinsic stress for interconnection structures. Since W has a low mobility at its depo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::becd134bbb5a073643b3d95c24f3433c
https://doi.org/10.1557/proc-391-115
https://doi.org/10.1557/proc-391-115
Autor:
Paul T. Herrington, Bruce Woolery
Publikováno v:
Optical/Laser Microlithography III.
Process Induced Distortion (PID) was characterized on a Non-thermally Ramped N channel Logic technology. Worst case registration locations were identified by mapping 120 registration sites per wafer on 8 wafers with a Quaestor measuring system. Final
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eadc4a5fc88ea35cf0c5bb3e8c21194
https://doi.org/10.1117/12.20179
https://doi.org/10.1117/12.20179
Autor:
T. Raz, D. Pivin, M. Agostinelli, W. Yang, Kaizad Mistry, S. Jacobs, Yih Wang, S. Johnson, S. Pae, G. Subramanian, J. Sandford, J. Xu, Pramod Kolar, J. Jopling, M. Jones, C. Peterson, Kevin Zhang, M. DiBattista, B. Lee, M. Mehalel, Bruce Woolery, J. Hicks
Publikováno v:
Scopus-Elsevier
Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0c98cc931a027fc044917ca28e022450
http://www.scopus.com/inward/record.url?eid=2-s2.0-33846061871&partnerID=MN8TOARS
http://www.scopus.com/inward/record.url?eid=2-s2.0-33846061871&partnerID=MN8TOARS
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