Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Bruce Petrick"'
Autor:
Changku Hwang, Jinuk Luke Shin, A S Leon, K.W. Tam, Timothy P. Johnson, Dawei Huang, Hongping Li, A. Strong, Francis Schumacher, Bruce Petrick, Ha Pham, A. Smith
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:131-144
This fourth generation UltraSPARC T3 SoC processor implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable up to 512 threads in a 4-w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3cae5c740667a305aa9d7bb337d0927a
https://doi.org/10.1109/jssc.2010.2080491
https://doi.org/10.1109/jssc.2010.2080491
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:1815-1820
Dual on-chip 512-KB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13-/spl mu/m technology. Each 512-KB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 1.3 V and 85/spl deg/C. Thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a56a25182b36ef2f9264dfc5462652f7
https://doi.org/10.1109/jssc.2005.852165
https://doi.org/10.1109/jssc.2005.852165
Autor:
V. Mathur, Howard L. Levy, D. Bistry, Bruce Petrick, Ana Sonia Leon, Jinseung Son, Ha Pham, Mandeep Singh, Jinuk Luke Shin, U. Nair, Toshinari Takayanagi, N. Moon, Jeffrey Y. Su
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:7-18
A dual-core 64-bit microprocessor optimized for compute-dense systems such as rack-mount and blade servers for network computing was developed. The chip consists of two UltraSPARC II cores, each with its own 512 kB L2 cache, a DDR-1 memory controller
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::602dcbf853e5301e4c26da81905b2139
https://doi.org/10.1109/jssc.2004.838023
https://doi.org/10.1109/jssc.2004.838023
Publikováno v:
2010 IEEE Asian Solid-State Circuits Conference.
This fourth generation UltraSPARC T3 SoC processor (code named Rainbow Falls) implements sixteen 8-threaded SPARC cores to double on-chip thread count and throughput performance over its previous generation. It enhances glueless scalability to enable
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::624afbadd6bf90c41a4febb8bf175582
https://doi.org/10.1109/asscc.2010.5716541
https://doi.org/10.1109/asscc.2010.5716541
Autor:
Jinuk Luke Shin, David J. Greenhill, Kenway Tam, Ana Sonia Leon, Francis Schumacher, Dawei Huang, Allan Strong, Alan Smith, Bruce Petrick, Changku Hwang, Timothy Johnson, Hongping Li, Ha Pham
Publikováno v:
ISSCC
This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::443e01e44955fd737aaeaa4caf15b0df
https://doi.org/10.1109/isscc.2010.5434030
https://doi.org/10.1109/isscc.2010.5434030
Autor:
Mandeep Singh, Heesung Choi, Bruce Petrick, Vikas Mathur, Ana Sonia Leon, Jinuk Luke Shin, Jung-Cheng Yeh, Howard L. Levy, Vipin Gupta, T. Ziaja, Jinseung Son
Publikováno v:
CICC
Dual on-chip 512 kB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13 /spl mu/m technology. Each 512 kB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 13 V and 85 C. This fully i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6146c18e06e63a3452143b5c2e10cb6d
https://doi.org/10.1109/cicc.2004.1358818
https://doi.org/10.1109/cicc.2004.1358818
Publikováno v:
DAC
A processor core, previously implemented in a 0.25 μm AI process, is redesigned for a 0.13 μ m Cu process to create a dualcore processor with 1MB integrated L2 cache, offering an efficient performance/power ratio for compute-dense server applicatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::998b79040dd62a5c3d1f50be6dd6553a
https://doi.org/10.1145/996566.996750
https://doi.org/10.1145/996566.996750