Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Bruce B. Pedersen"'
Autor:
Mark Bourgeault, David Galloway, Gregg William Baeckler, Elias Ahmed, Andy L. Lee, David Lewis, Boris Ratchev, Sandy Marquardt, Christopher F. Lane, Richard G. Cliff, Srinivas T. Reddy, Bruce B. Pedersen, Michael D. Hutton, Jay Schleicher, Paul Leventis, Giles Powell, Cameron McClintock, Kevin Stevens, David Cashman, Jonathan Rose, Ketan Padalia, Vaughn Betz, Richard Yuan
Publikováno v:
FPGA
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits cont
Autor:
Andy L. Lee, David Lewis, Boris Ratchev, Rahul Saini, Sinan Kaptanoglu, Jay Schleicher, Ketan Padalia, Gregg William Baeckler, Bruce B. Pedersen, Michael D. Hutton, Henry Kim, Richard Yuan, Mark Bourgeault
Publikováno v:
Field Programmable Logic and Application ISBN: 9783540229896
FPL
FPL
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09ec0ab9a1ce8489895ee7fda52ba1f1
https://doi.org/10.1007/978-3-540-30117-2_16
https://doi.org/10.1007/978-3-540-30117-2_16
Autor:
Srinivas T. Reddy, David Lewis, Paul Leventis, Giles Powell, Richard G. Cliff, Christopher F. Lane, Chris Wysocki, Sandy Marquardt, Cameron McClintock, Andy L. Lee, David Jefferson, Bruce B. Pedersen, Jonathan Rose, Vaughn Betz
Publikováno v:
FPGA
This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing archit
Autor:
C. McClintock, John E. Turner, A. Lee, David Jefferson, Richard G. Cliff, R. Altaf, Bruce B. Pedersen, J. Schleicher, K. Zaveri, M. Mejia, Christopher F. Lane, Srinivas T. Reddy, Frank Heile, N. Ngo
Publikováno v:
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
Altera has developed a next generation architecture called APEX/sup TM/ to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system
Autor:
V. Singhal, A. Gupta, Kerry Veenstra, Joseph Huang, Craig Schilling Lytle, Ricky W. Ho, Srinivas T. Reddy, Frank Heile, S. Mashruwala, Rina Raman, C.K. Sung, Bruce B. Pedersen, L.T. Cope, Richard G. Cliff, Bahram Ahanin
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.
A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity a
Autor:
Khai Nguyen, John E. Turner, Kerry Veenstra, Richard G. Cliff, Joseph Huang, Chiakang Sung, Bonnie I. Wang, Xiaobao Wang, Bruce B. Pedersen
Publikováno v:
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
An SRAM based PLD architecture ranging from 5000 to 24000 gates has been developed. The primary focus of the architecture is on low cost, high performance, and routability. Breakthroughs in interconnect scheme have been made to achieve flexible routi
Autor:
Jim Park, Michael D. Hutton, Bruce B. Pedersen, Vinson Chan, Sergey Shumarayev, Jay Schleicher, Rakesh H. Patel, Tony Ngai, Peter J. Kazarian, Victor Maruri
Publikováno v:
FPGA
As programmable logic grows more viable for implementing full design systems, performance has become a primary issue for programmable logic device architectures. This paper presents the high-level design of Dali, a PLD architecture specifically aimed
Publikováno v:
FPGA
Architects of programmable logic devices (PLDs) face several challenges when optimizing a new device family for low manufacturing cost. When given an aggressive die-size goal, functional blocks that seem otherwise insignificant become targets for are