Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Brian Hornung"'
Autor:
Shaofeng Yu, Brian K. Kirkpatrick, O'brien Corey Rollin, Larry Liu, Rajesh Khamankar, Oluwamuyiwa Oluwagbemiga Olubuyide, Deborah J. Riley, Anand T. Krishnan, I. Fujii, C. Machala, Clinton L. Montgomery, Brian Hornung, H. Bu, Yiming Gu, Steven L. Prins, T. Lowry, K. Kirmse, James Walter Blatchford, Tad Grider, C. Bowen, G. Shinn, D. Corum, C. Lin, Tony Tae-Hyoung Kim
Publikováno v:
2008 Symposium on VLSI Technology.
A 45 nm high performance technology with 11 level metallization is presented for SOC applications. High performance and density are maintained through new process optimizations that allow the use of less restrictive layouts by eliminating defect gene
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e24ec331746ae0843044248c5da8aaa5
https://doi.org/10.1109/vlsit.2008.4588608
https://doi.org/10.1109/vlsit.2008.4588608
Autor:
Rajesh Khamankar, Joe G. Tran, P.E. Nicollian, Anand T. Krishnan, Melissa M. Hewson, S. Aur, Mark Somervell, James Walter Blatchford, Tad Grider, Lindsey H. Hall, Brian K. Kirkpatrick, D. Farber, Srinivasan Chakravarthi, Benjamen Michael Rathsack, H. Bu, Brian Hornung, Juanita Deloach, Brian A. Smith, Jiong-Ping Lu, C. Kaneshige, April Gurba, C. Bowen, C. Machala, Donald S. Miles, Husam N. Alshareef, M. J. Bevan, P.R. Chidambaram, Vladimir A. Ukraintsev, Ajith Varghese, Hiroaki Niimi
Publikováno v:
Scopus-Elsevier
In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7bea0f7129ea088a7c5308d5ef089297
https://doi.org/10.1109/vlsit.2004.1345456
https://doi.org/10.1109/vlsit.2004.1345456
Publikováno v:
Simulation of Semiconductor Processes and Devices 2004 ISBN: 9783709172124
Indium (In) diffusion and dose-loss in silicon is modeled in a continuum simulator. The model includes the large segregation of In to End of Range (EOR) defects, and the dissolution of these defects resulting in dose-loss of In at the surface. The mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a085ff5763c2b2fb65844f30bbc3af5
https://doi.org/10.1007/978-3-7091-0624-2_12
https://doi.org/10.1007/978-3-7091-0624-2_12
Autor:
P.R. Chidambaram, Brian Hornung, Amitabh Jain, Srinivasan Chakravarthi, H. Bu, P. Kohli, C. Machala
Publikováno v:
International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..
A novel model is developed to explain the effect of the source/drain sidewall spacer process on boron drain extension formation. A diffusion model for hydrogen in the source/drain sidewall spacer is developed and combined with a model for boron diffu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::03d9e73517ad36d8191101d6ab1952b3
https://doi.org/10.1109/sispad.2003.1233661
https://doi.org/10.1109/sispad.2003.1233661
Autor:
Husam N. Alshareef, Juanita Deloach, M. J. Bevan, C. Bowen, M. Goodwin, P.R. Chidambaram, James Walter Blatchford, Srinivasan Chakravarthi, Tad Grider, Brian K. Kirkpatrick, Rajesh Khamankar, April Gurba, Ajith Varghese, Hiroaki Niimi, Donald S. Miles, Brian A. Smith, Xin Zhang, C. Machala, Jiong-Ping Lu, Lance S. Robertson, G.V. Thakar, Benjamen Michael Rathsack, Brian Hornung, P.E. Nicollian
Publikováno v:
2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f9fff4d3ed93400052c81221e1ec69b
https://doi.org/10.1109/vlsit.2003.1221098
https://doi.org/10.1109/vlsit.2003.1221098