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pro vyhledávání: '"Brian Elies"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:3235-3247
A process, voltage, and temperature (PVT)-stabilized dynamic amplification technique is reported for the pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC). A non-interleaved 12-b 330-MS/s pipelined-SAR ADC prototype
Autor:
Shih Wei-Yan, Suman Bellary, Michael Zwerg, Scott R. Summerfelt, Nagaraj Krishnasawamy, Sudhanshu Khanna, Juergen Luebbe, Steven Bartling, Brian Elies, Hadi Najar
Publikováno v:
ISSCC
Ultra-low Power Microcontrollers (MCUs) [1]–[4] have played a central role in embedded IoT systems providing programmability, analog and digital processing and control, A/D interfaces, and power management. As IoT applications expand, efficient sen
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:654-661
A digital background calibration technique to treat capacitor mismatch, residue gain error, and nonlinearity in a pipelined ADC based on the split-ADC architecture is reported. Although multiple works have been reported before on the split- calibrati
Publikováno v:
MWSCAS
An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue ampli
Publikováno v:
ISSCC
In high-speed pipeline or pipelined-SAR ADCs, conventional opamp-based residue amplifiers consume significant amounts of power due to stringent settling speed and accuracy requirements. A recent alternative approach employs a dynamic amplifier [1] to
Publikováno v:
VLSIC
A 1-0 MASH ΔΣ ADC demonstrates a digital calibration technique treating both amplifier distortion and capacitor mismatch. The output-referred error analysis accurately models a nonlinear modulator. The identification of multiple error parameters is