Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Brian E. Stine"'
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 16:259-265
Complexity of integrated circuits has led to many millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of < 10 faults per billion which requires test structures with huge chains of 1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1b6db3a6fe5d5195341190e23f575d7
https://doi.org/10.1109/tsm.2003.811939
https://doi.org/10.1109/tsm.2003.811939
Publikováno v:
VTS
The onset of FinFET technology nodes brings with it additional challenges in ramping yields due to new defect behaviors and new hardships in the physical failure analysis process. This presentation highlights these challenges and makes the argument t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ee5da94757d0851dab11bde13a3d4a2
https://doi.org/10.1109/vts.2014.6818749
https://doi.org/10.1109/vts.2014.6818749
Autor:
Larg Weiland, Christopher Hess, K. Miyamoto, D. Stashower, Gaurav Verma, K. Inoue, Brian E. Stine
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 14:330-337
Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7d36a5ecbcc2e94bee809d4edd22b1c
https://doi.org/10.1109/66.964320
https://doi.org/10.1109/66.964320
Publikováno v:
2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
Random defectivity reduction is an important prerequisite to achieving mature production yields. The typical technology roadmap includes a product yield / defect density reduction curve over the technology lifetime. Translating the defect density red
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f441bde001a21db1e19031050013305
https://doi.org/10.1109/asmc.2008.4529012
https://doi.org/10.1109/asmc.2008.4529012
Publikováno v:
2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Typically equipment PM optimization and strategy is determined using a mix of various sources and inline inspection. In this work, the need for a more yield aware optimization strategy is recognized and recommendations made to implement this.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85aad55677b6bd91b65514630087a36d
https://doi.org/10.1109/asmc.2007.375098
https://doi.org/10.1109/asmc.2007.375098
Publikováno v:
The 17th Annual SEMI/IEEE ASMC 2006 Conference.
An effective yield ramp methodology is demonstrated using fail signature detection algorithm (FSDA). Wafers with similar yield spatial patterns are grouped together to find stronger correlations to equipment data. Many signals that would have been mi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b41f2a5619c1305bac27ec3b33b8af0
https://doi.org/10.1109/asmc.2006.1638757
https://doi.org/10.1109/asmc.2006.1638757
Publikováno v:
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002..
Manufacturing of integrated circuits relies on the sequence of many hundred process steps. Each of these steps will have more or less variation, which has to be within a,certain limit to guarantee the chips functionality at a target speed. But, not e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22664aba1ca120f5202da83842f71aa4
https://doi.org/10.1109/icmts.2002.1193195
https://doi.org/10.1109/icmts.2002.1193195
Autor:
Brian E. Stine, Christopher Hess, K. Miyamoto, G. Verna, Larg Weiland, D. Stashower, K. Inoue
Publikováno v:
ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095).
Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size di
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3d15d53a548d97897477667f2fb6ef9a
https://doi.org/10.1109/icmts.2000.844405
https://doi.org/10.1109/icmts.2000.844405
Autor:
Roland Ruehl, Rakesh Vallishayee, Wojtek Wojciak, Dennis Ciplickas, Mariusz Niewczas, Brian E. Stine
Publikováno v:
SPIE Proceedings.
This paper presents the result of an extension to the concept of Micro-Yield modeling. We have developed a design attribute extraction and yield prediction software system that - given the characterization of a semiconductor process via complex test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da21c0ed4cc0c39c11abcc73328a0e5d
https://doi.org/10.1117/12.475671
https://doi.org/10.1117/12.475671
Conference
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