Zobrazeno 1 - 10
of 74
pro vyhledávání: '"Brady Benware"'
Publikováno v:
DFT
Earlier works showed that the resolution of defect diagnosis when multiple defects are present in a chip can be improved by instructing the defect diagnosis procedure to ignore certain tests. Specifically, these procedures reduce the number of candid
Publikováno v:
ATS
Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. It was reported in prior papers that about 30% to 50% of all failing die were due to defects that cause scan chains to fail [1][2]. Ther
Autor:
Sudhakar M. Reddy, Randy Klingenberg, Manish Sharma, Yue Tian, Geir Eide, Atul Chittora, Wu-Tung Cheng, Yan Pan, Sherwin Fernandes, Wu Yang, Brady Benware
Publikováno v:
ATS
in many cases, the main cause of yield loss is a specific layout pattern that is difficult to manufacture and is prone to causing an open or short defect. This situation is getting worse with advanced technology nodes due to small feature sizes and c
Publikováno v:
IEEE Design & Test of Computers. 29:8-18
The yield of an integrated circuit (IC) is well known to be a critical factor in the success of an IC in the market place. Achieving high stable yields helps ensure that the product is profitable and meets quality and reliability objectives. When a n
Autor:
Yi-Jung Chang, Man-Ting Pang, Mike Brennan, Albert Man, Martin Keim, Geir Eide, Brady Benware, Ting-Pu Tai
Publikováno v:
EDFA Technical Articles. 12:12-18
This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test resul
Publikováno v:
IEEE Design & Test of Computers. 27:54-61
The cost and cycle time for determining the root cause of yield loss continues to increase as semiconductor technology scales down. A new technique, Axiom, helps yield and product engineers determine the root cause of loss directly from diagnosis res
Publikováno v:
VLSI-DAT
The semiconductor industry is encountering an increasing number of front-end-of-line defects in the advanced FinFET technology nodes due to extremely small feature size and complex manufacturing processes required for FinFET transistors. Traditional
Autor:
Brady Benware, W. Maly, R.D. Blanton, C. Schuermyer, T. Zanon, J.E. Nelson, J.G. Brown, O. Poku
Publikováno v:
IEEE Design & Test of Computers. 23:390-400
Defect density and size distributions (DDSDs) are important parameters for characterizing spot defects in a process. This article addresses random spot defects, which affect all processes and currently require a heavy silicon investment to characteri
Publikováno v:
IEEE Design & Test of Computers. 23:100-109
The expanded role of test demands a significant change in mind-set of nearly every engineer involved in the screening of semiconductor products. The issues to consider range from DFT and ATE requirements, to the design and optimization of test patter
Autor:
Robert Tao, Friedrich Hapke, Huaxing Tang, Joseph Caroselli, Wu-Tung Cheng, Thomas Herrmann, M. Reese, Manish Sharma, Brady Benware
Publikováno v:
ATS
The industry is encountering an increasing number of front-end-of-line defects in the most advanced technology nodes due to extremely small feature size and complex manufacturing processes. Traditional scan diagnosis algorithms can locate a defective