Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Bradley McCredie"'
Autor:
Bradley McCredie, Wiren D. Becker
Publikováno v:
IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B. 19:461-472
The computer package designer depends on modeling power supply noises to ensure that system designs will function properly. Power supply noises can have a tremendous effect on system operation and performance. The circuit simulation of a system power
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::521080a66b2cc7b353ae02522638b111
https://doi.org/10.1109/96.533884
https://doi.org/10.1109/96.533884
Autor:
Bradley McCredie, Tim Kogel, Jason Cong, Eshel Haritan, John Paul Shen, Stan Krolikoski, Ruchir Puri, Andres Takach
Publikováno v:
DAC
This panel discusses power optimization at the system level. What are the needs and opportunities? What are examples of successful practices? Can system-level power optimizations ever be automated? Can power optimizations be the enabling event for a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdc8579f22f2444b575086a3ebb38398
https://doi.org/10.1145/1629911.1630105
https://doi.org/10.1145/1629911.1630105
Publikováno v:
ISSCC
The POWER6trade is a dual-core microprocessor fabricated in a 65nm SOI process with 10 levels of low-k copper interconnects. Chips with split- and connected-core power supplies are fabricated, modeled, and tested, showing both the advantages and disa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::593fb2915b844e0229be8ae61e8a8b07
https://doi.org/10.1109/isscc.2007.373412
https://doi.org/10.1109/isscc.2007.373412
Autor:
Gaurav Mittal, Scott A. Taylor, Bradley McCredie, Jack DiLullo, E. Chan, L. Clark, B. Huott, Sam Gat-Shang Chu, Norman Karl James, Y.H. Chan, M. Lanzerotti, J. Ripley, Brian W. Curran, Donald W. Plass, Joshua Friedrich, Hung Le, Eric Fluhr
Publikováno v:
ISSCC
The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microproces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::587a6002500c60fc57234643110e1bd5
https://doi.org/10.1109/isscc.2007.373605
https://doi.org/10.1109/isscc.2007.373605
Autor:
A. Goyal, Y.H. Chan, M. Vaden, Bruce M. Fleischer, Eric M. Schwarz, Brian W. Curran, L. Sigal, D. Webber, Bradley McCredie
Publikováno v:
ISSCC
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35a837302b45d717a6ffad727668a277
https://doi.org/10.1109/isscc.2006.1696229
https://doi.org/10.1109/isscc.2006.1696229
Autor:
Keith A. Jenkins, A.V. Mule, C.A. Carter, Alan J. Weger, Bradley McCredie, Byron L. Krauter, J.P. Eckhardt, Phillip J. Restle
Publikováno v:
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
The clock distribution on the Power4 dual-processor chip supplies a single critical 1.5 GHz clock from one SOI-optimized PLL to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18a12a53b89e70c0da71e2b05452c2c3
https://doi.org/10.1109/isscc.2002.992162
https://doi.org/10.1109/isscc.2002.992162
Publikováno v:
Proceedings of IEEE Electrical Performance of Electronic Packaging.
A methodology for obtaining a model of the power distribution of a computer package is presented. This model is suitable for determining the noise and aiding in the design of a computer package. The physical features of a typical first-level multi-la
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f9ff1799d1c43b075001ca348a48c382
https://doi.org/10.1109/epep.1993.394554
https://doi.org/10.1109/epep.1993.394554
Publikováno v:
Proceedings of 1994 IEEE Electrical Performance of Electronic Packaging.
The characterization of the simultaneous switching noise magnitude of 0.25 /spl mu/m channel CMOS drivers obtained through high-frequency measurements is presented in this paper.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7155d299b85116629b7d7661c7355d67
https://doi.org/10.1109/epep.1994.594096
https://doi.org/10.1109/epep.1994.594096
Publikováno v:
Proceedings of 1994 IEEE Electrical Performance of Electronic Packaging.
The simultaneous switching noise simulation and the comparison of those simulations to laboratory measurements of noise on a specially designed CMOS test chip on a multilayer ceramic SCM are presented.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f2789af91de9aeb1681222cb57a4c67c
https://doi.org/10.1109/epep.1994.594066
https://doi.org/10.1109/epep.1994.594066
Publikováno v:
Proceedings of Electrical Performance of Electronic Packaging.
Contrary to popular opinion, smaller feature sizes are not always faster when it comes to designing large custom CMOS die. This is due to the fact that at and below 0.5 micron ground rules, metal line cross-sections are becoming so small that lossy l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6d73def47f0b4d22d306ea7a4813dc3
https://doi.org/10.1109/epep.1995.524682
https://doi.org/10.1109/epep.1995.524682