Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Boya Pradeep Kumar"'
Publikováno v:
Applied Science and Engineering Progress.
The multi-processor cores in SoC which have high burst data transactions can play a critical role while accessing the shared resources such as the off-chip memory. These processor cores can starve other processor cores that have less burst data trans
Publikováno v:
SN Computer Science; October 2024, Vol. 5 Issue: 7
Publikováno v:
Emerging Trends in Electrical, Electronic and Communications Engineering ISBN: 9783319521701
Finite-difference time-domain (FDTD) is a versatile modeling technique which employs finite differences as approximations to both spatial and temporal derivatives. It is a numerical analysis technique used for modeling electrodynamics. The FDTD model
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1593b5ed11714565db2a08d75c7960ce
https://doi.org/10.1007/978-3-319-52171-8_17
https://doi.org/10.1007/978-3-319-52171-8_17
Autor:
Chandra Sekhar Paidimarry, Sowmya Todima, Boya Pradeep Kumar, Sreehitha Ghuguloth, Sumanjali Pastham
Publikováno v:
2016 International Conference on Signal and Information Processing (IConSIP).
Clock and data recovery (CDR) circuit plays a vital role for wired serial link communication in multi mode based system on chip (SOC). In wire linked communication systems, when data flows without any accompanying clock over a single wire, the receiv
Publikováno v:
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).
Turbo coding is a powerful error correction technique among forward error correcting codes. Its performance is better as it achieves near Shannon limit. This paper presents the implementation of Turbo codec for designing the Turbo encoder and decoder
Publikováno v:
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).
Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. I
Publikováno v:
International Conference on Computing and Communication Technologies.
Adders play an important role in digital circuits. Logarithmic adders are efficient in delay reduction of carry generation/propagation in contrary to linear adders. It is found from simulations that even logarithmic adders suffer from delay, chip are
Publikováno v:
CSNDSP
This paper proposes a computationally efficient explicit finite difference time domain (FDTD) scheme for the TEz mode. In contrary to conventional FDTD method, we derive the finite difference of magnetic field using asymmetric approximation to the se
Publikováno v:
2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy.
Conventionally, Specific Absorption Rate (SAR) to a cancer tumor is estimated using an inaccurate water phantom method in hospitals. In this paper, we propose an accurate SAR estimation method using Finite Difference Time Domain (FDTD) technique. The
Publikováno v:
2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia); 2015, p9-15, 7p