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pro vyhledávání: '"Bouchez, Florent"'
Autor:
Bouchez, Florent
Le but de l'allocation de registres est d'assigner les variables d'un programme aux registres ou de les " spiller " en mémoire s'il n'y a plus de registre disponible. La mémoire est bien plus lente, il est donc préférable de minimiser le spilling
Externí odkaz:
http://tel.archives-ouvertes.fr/tel-00403504
http://tel.archives-ouvertes.fr/docs/00/41/41/22/PDF/thesis-final.pdf
http://tel.archives-ouvertes.fr/docs/00/41/41/22/PDF/thesis-final.pdf
Publikováno v:
ACM SIGPLAN Notices Issue 7, Volume 42 (2007) 103 - 112
Compilation for embedded processors can be either aggressive (time consuming cross-compilation) or just in time (embedded and usually dynamic). The heuristics used in dynamic compilation are highly constrained by limited resources, time and memory in
Externí odkaz:
http://arxiv.org/abs/0710.3642
Autor:
Bouchez, Florent.
Th.--Méd.--Paris, 1905-1906.
Paris, 1905-1906, tome 6, n ° 461.
Paris, 1905-1906, tome 6, n ° 461.
Externí odkaz:
http://catalogue.bnf.fr/ark:/12148/cb36858357b
Autor:
Bouchez, Florent
Publikováno v:
Autre [cs.OH]. Ecole normale supérieure de lyon-ENS LYON, 2009. Français. ⟨NNT : ⟩
Autre [cs.OH]. Ecole normale supérieure de lyon-ENS LYON, 2009. Français
Autre [cs.OH]. Ecole normale supérieure de lyon-ENS LYON, 2009. Français
Version finale (7 septembre 2009); The goal of register allocation is to assign the variables of a program to the registers or to spill them to memory whenever there are no register left. Since memory is much slower than registers, it is best to mini
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1bce22a716e0d25470d479a4b4a619a3
https://theses.hal.science/tel-00403504
https://theses.hal.science/tel-00403504
Publikováno v:
Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, 2008, pp.147-156. ⟨10.1145/1450095.1450119⟩
Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, 2008, pp.147-156. ⟨10.1145/1450095.1450119⟩
18 pages; International audience; Register coalescing is used, as part of register allocation, to reduce the number of register copies. Developing efficient register coalescing heuristics is particularly important to get rid of the numerous move inst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::076587c8a86c3d743c57ce6dfc98f75d
https://hal-ens-lyon.archives-ouvertes.fr/ensl-00179685/file/main-RR-LIP.pdf
https://hal-ens-lyon.archives-ouvertes.fr/ensl-00179685/file/main-RR-LIP.pdf
Publikováno v:
[Research Report] LIP RR-2006-13, Laboratoire de l'informatique du parallélisme. 2006, 2+12p
Register allocation is one of the most studied problem in compilation. It is consideredas an NP-complete problem since Chaitin, in 1981, showed that assigning temporary variablesto k machine registers amounts to color, with k colors, the interference
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::723e4ceb023c60e702a31ad774115d76
https://hal-lara.archives-ouvertes.fr/hal-02102286/document
https://hal-lara.archives-ouvertes.fr/hal-02102286/document
Publikováno v:
[Research Report] Laboratoire de l'informatique du parallélisme. 2005, 2+28p
This report deals with the problem of choosing which variables to spill during the register allocation phase. Spilling is used when the number of variables is higher than the number of registers, and consists of storing the value of a variable in mem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::55dc8195a1583409d4f67e0320406a4a
https://hal-lara.archives-ouvertes.fr/hal-02102197/document
https://hal-lara.archives-ouvertes.fr/hal-02102197/document
Publikováno v:
[Research Report] LIP RR-2004-16, Laboratoire de l'informatique du parallélisme. 2004, 3+25p
Instruction cache performance is one of the bottle-necks of processor performance. In this paper, we study the effects of procedure placement in memory on a direct-mapped instruction cache. These caches differ from associative memory caches by the fa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::1f286aa9203fc59cf5434ee0d1099fc7
https://hal-lara.archives-ouvertes.fr/hal-02101989/file/RR2004-16.pdf
https://hal-lara.archives-ouvertes.fr/hal-02101989/file/RR2004-16.pdf
Publikováno v:
Proceedings of the 13th International Workshop: Software & Compilers for Embedded Systems; 6/28/2010, p1-10, 10p
Publikováno v:
Proceedings of the 2008 International Conference: Compilers, Architectures & Synthesis for Embedded Systems; 10/19/2008, p147-156, 10p