Zobrazeno 1 - 10
of 66
pro vyhledávání: '"Boualem Djezzar"'
Publikováno v:
IEEE Transactions on Electron Devices. 68:2181-2188
In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the p
Publikováno v:
IEEE Transactions on Electron Devices. 68:2173-2180
In this article, we report a new capacitance–voltage technique ${C}$ ( ${V}$ ) to investigate the interface proprieties of MOS devices. This technique is based on surface potential modulation using time varying (ac) magnetic field. It is experiment
Autor:
Boualem Djezzar, Mohamed Boubaaya, Abdelkader Zitouni, Abdelmadjid Benabdelmoumene, Dhiaelhak Messaoud, Boumediene Zatout
Publikováno v:
Algerian Journal of Signals and Systems. 6:24-31
To measure the entire characteristic of p-MOSFET, we have implemented the fast Ids-Vgs technique. The latter is used to study NBTI phenomenon with measure-stress-measure method, for electric field 5MV/cm < Eox < 7.5MV/cm, and temperatures 27°C < Ts
Autor:
Boualem Djezzar, Ali HOUADEF
Publikováno v:
Algerian Journal of Signals and Systems. 6:16-23
Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. The device under test is obtained from process simulation under a 1µm CMOS flow available at CDTA. The n-type transistor uses the LOCOS (local oxidation of si
Autor:
Alessio Spessot, Mohamed Boubaaya, Pierre C. Fazan, Barry O'Sullivan, E. Dupuy, J. Franco, V. Machkaoutsan, A. Ferhat Hamida, Eugenio Dentoni Litta, Cheolgyu Kim, Djamila Bennaceur-Doumaz, Romain Ritzenthaler, D. Linten, Boualem Djezzar, Naoto Horiguchi
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 20:269-277
Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high- $\kappa $ metal gate (HKMG) FinFET transistors is reported for the first time. It was observed that NBTI degradation is less seve
Publikováno v:
IET Circuits, Devices & Systems. 14:555-561
This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS acce
Autor:
Boualem Djezzar, Ali HOUADEF
Publikováno v:
ICCEIS 2021.
Autor:
Boualem Djezzar, Ali HOUADEF
Publikováno v:
ICCEIS 2021.
Autor:
A. Houadef, Boualem Djezzar
Publikováno v:
2021 IEEE 32nd International Conference on Microelectronics (MIEL).
This work investigates by TCAD simulation the impact of hot carrier degradation (HCD) in an nLDMOS that uses many topological features. The trenched gate and the triple-RESURF used to optimally reduce the device on-resistance $(R_{ON})$ , triggers DC
Autor:
Ali Houadef, Boualem Djezzar
Publikováno v:
International Journal of RF and Microwave Computer-Aided Engineering. 31