Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Boris Ratchev"'
Publikováno v:
FPL
The design of FPGA architectures involves optimization of area, delay, power and routability across hundreds of architectural choices (e.g. LUT size, wire length, flexibility and circuit sizing). Since the difficulty of defining and predicting the de
Autor:
Mark Bourgeault, David Galloway, Gregg William Baeckler, Elias Ahmed, Andy L. Lee, David Lewis, Boris Ratchev, Sandy Marquardt, Christopher F. Lane, Richard G. Cliff, Srinivas T. Reddy, Bruce B. Pedersen, Michael D. Hutton, Jay Schleicher, Paul Leventis, Giles Powell, Cameron McClintock, Kevin Stevens, David Cashman, Jonathan Rose, Ketan Padalia, Vaughn Betz, Richard Yuan
Publikováno v:
FPGA
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits cont
Autor:
Andy L. Lee, David Lewis, Boris Ratchev, Rahul Saini, Sinan Kaptanoglu, Jay Schleicher, Ketan Padalia, Gregg William Baeckler, Bruce B. Pedersen, Michael D. Hutton, Henry Kim, Richard Yuan, Mark Bourgeault
Publikováno v:
Field Programmable Logic and Application ISBN: 9783540229896
FPL
FPL
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09ec0ab9a1ce8489895ee7fda52ba1f1
https://doi.org/10.1007/978-3-540-30117-2_16
https://doi.org/10.1007/978-3-540-30117-2_16
Publikováno v:
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays.
Though verification is significantly easier for FPGA-based digital systems than for ASIC or full-custom hardware, there are nonetheless many places for errors to occur.In this paper we discuss the verification problem for FPGAs and describe several m