Zobrazeno 1 - 10 of 557 pro vyhledávání: '"Booth's multiplication algorithm"'
2
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications
Autor: Ch. Keshava Gopal, K. Manikantta Reddy, Devesh Dwivedi, M H Vasantha, Y B Nithin Kumar
Publikováno v: Integration. 81:268-279
Approximate computing has emerged as an efficient design methodology for improving the performance and power-efficiency of digital systems by allowing a negligible loss in the output accuracy. Dedicated hardware accelerators built using approximate c
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fa2ce7c6a1f8b9bb8f0cb429be763cbd
https://doi.org/10.1016/j.vlsi.2021.08.001
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3
A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs
Autor: Qing Liu, Guangsen Wang, Bin Zhou, Guisheng Jie, Wang Zhiwei
Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29:1782-1789
In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed. It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC). The multiplier is realized by a radix-4 Booth encoding based on s
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6c7402fe51b0e36850feaebc8303f733
https://doi.org/10.1109/tvlsi.2021.3105268
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5
Analysis of Existing and Proposed 3-Bit and Multi-Bit Multiplier Algorithms for FIR Filters and Adaptive Channel Equalizers on FPGA
Autor: Muhammad Awais Rajput, Aneela Pathan, Fareesa Khan Sohu, Tayab Din Memon
Publikováno v: Quaid-e-Awam University Research Journal of Engineering Science & Technology. 19:81-89
Different multiplication algorithms have different performance characteristics. Some are good at speed while others consume less area when implemented on hardware, like Field Programmable Gate Array (FPGA)-the advanced implementation technology for D
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::249ecc53bcdf83448e61aab9fc93730d
https://doi.org/10.52584/qrj.1901.12
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6
An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes
Autor: B. Paramasivan, N. Arumugam
Publikováno v: Multidimensional Systems and Signal Processing. 32:1277-1311
The Finite Impulse Response (FIR) filter plays an important role in many signal processing applications. This manuscript proposes an intuitive adaptive filter based on fixed-point finite impulse response with approximate distributed arithmetic (DA) c
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d94861a68e5e1867c2675a86c8383027
https://doi.org/10.1007/s11045-021-00783-y
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7
Design of an Improved Low-Power and High-Speed Booth Multiplier
Autor: Shabbir Majeed Chaudhry, Ahsan Rafiq
Publikováno v: Circuits, Systems, and Signal Processing. 40:5500-5532
This paper presents an improved 8 × 8-bit Booth multiplier with reduced power, delay and area. The major operations that consume power and are responsible for larger critical path delays in Booth multiplication are partial product array generation (
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a4be319da624b50c25ba68343fd28196
https://doi.org/10.1007/s00034-021-01730-9
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8
Analysis and Design of a High Performance Radix-4 Booth Scheme in CMOS Technology
Autor: Ali Rahnamaei
Publikováno v: Majlesi Journal of Telecommunication Devices. 10:67-73
In this paper, a novel high performance structure has been demonstrated which can be widely used for circuit-level realization of radix-4 Booth scheme. The notable privilege of proposed scheme is its higher speed for generation of Partial Products (P
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e83b1be46c02d130e61eadaaa486224c
https://doi.org/10.52547/mjtd.10.2.67
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9
Implementation and Comparison of Radix-8 Booth Multiplier by using 32-bit Parallel prefix adders for High Speed Arithmetic Applications
Autor: Barma Venkata RamaLakshmi et. al.
Publikováno v: Turkish Journal of Computer and Mathematics Education (TURCOMAT). 12:5673-5683
This paper presents the implementation and design of Radix-8 booth Multiplier using 32-bit parallel prefix adders. High performance processors have a high demand in the industrial market. For achieving high performance and to enhance the computationa
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c10fbcd413800b69421e2bc33d1d0e36
https://doi.org/10.17762/turcomat.v12i3.2242
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10
Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology
Autor: Yuan-Ho Chen
Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 68:1018-1022
In this brief, we propose a data scaling technology (DST) for use in a low-error fixed-width Booth multiplier (FWBM) to reduce truncation errors. The proposed DST reduces the number of redundant bits in the multiplicand, yielding more efficient bits
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::776101d903b395efe94374b6b2ee799e
https://doi.org/10.1109/tcsii.2020.3023429
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