Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Boonchuay Supmonchai"'
Publikováno v:
2023 International Electrical Engineering Congress (iEECON).
Autor:
Kan Pinyotrakool, Boonchuay Supmonchai
Publikováno v:
2020 8th International Electrical Engineering Congress (iEECON).
A low power processor for embedded systems is designed and implemented. The proposed processor can operate on RV32E instruction set architecture using a modified MIPS micro-architecture. Clock gating technique and Standby mode are applied to reduce p
Publikováno v:
2018 15th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).
This paper presents an input capacitor-less boost converter with a maximum power point tracking (MPPT) circuit for thermal energy harvesting applications. The MPPT circuit is implemented by a fractional open-circuit voltage method with a feedback con
Publikováno v:
2018 International Electrical Engineering Congress (iEECON).
This paper presents the circuit level design of a CMOS low power limiting amplifier with received signal strength indicator (RSSI) for low frequency application. The design utilizes a five-stage cascade amplifier with PMOS double diode-connected load
Publikováno v:
Applied Mechanics and Materials. 781:151-154
This paper presents an FPGA architecture for the 1-D integer transform of the latest video coding standard, the High Efficiency Video Coding (HEVC). The design employs hard multipliers in dedicated DSP slices, which are already embedded into an FPGA
Publikováno v:
2015 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON).
This paper proposes an FPGA architecture for the 1-D forward integer transform of the High Efficiency Video Coding (HEVC), which is the latest video coding standard. The work presents a novel technique which makes the architecture able to compute tra
Publikováno v:
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
The capacitor-less LDO regulator with slew-rate enhancement disabling scheme has been introduced and postlayout simulated in 2P4M 0.35-μm CMOS process. The output voltage can be adjusted on-the-fly from 0.9 to 1.6 V with minimum supply voltage of 1.
Publikováno v:
Proceedings of IEEE International Conference on Teaching, Assessment, and Learning for Engineering (TALE) 2012.
Teamwork assessment by peers in small groups could be affected by personal relationships. This paper presented a system of teamwork assessments for a postgraduate course in a Thai university that integrated the collaborative learning and hand-on grou
Publikováno v:
Applied optics. 39(23)
The design of a fiber-optic local area network (LAN) demonstration system is described. A complete LAN system would consist of an array of 16 personal computers (PC’s), where each PC has a network interface card (NIC) with a parallel fiber-optic da
Publikováno v:
Applied optics. 39(5)
A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as