Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Bok-Moon Kang"'
Autor:
Wenqi Wang, Sang Don Yi, Fu Li, Qingchen Cao, Jiangliu Shi, Bok-Moon Kang, Meichen Jin, Chang Liu, Zhenhua Wu, Guilei Wang, Chao Zhao
Publikováno v:
IEEE Access, Vol 12, Pp 46504-46511 (2024)
In this article, a honeycomb vertical surrounding gate access transistor array scheme is proposed to further decrease the DRAM cell area with aggressively shrink bit line (BL) pitch and word line (WL) pitch adopting the ZigZag BL and WL air gap. To v
Externí odkaz:
https://doaj.org/article/61949f02cf1c45d788be48584082702e
Autor:
Wendong Lu, Zhengyong Zhu, Kaifei Chen, Menggan Liu, Bok-Moon Kang, Xinlv Duan, Jiebin Niu, Fuxi Liao, Wang Dan, Xie-Shuai Wu, Joohwan Son, De-Yuan Xiao, Gui-Lei Wang, Abraham Yoo, Kan-Yu Cao, Di Geng, Nianduan Lu, Guanhua Yang, Chao Zhao, Ling Li, Ming Liu
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Autor:
Zheng-Yong Zhu, Bok-Moon Kang, Wang Dan, Xie-Shuai Wu, Joohwan Son, Yong Yu, De-Yuan Xiao, Jin Dai, Gui-Lei Wang, Abraham Yoo, Kan-Yu Cao, Chao Zhao
Publikováno v:
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).
Autor:
Keum-Yong Kim, Ejaz Haq, Kye-Hyun Kyung, Kinam Kim, Bok-Moon Kang, Moon-Hae Son, Chang-Hyun Kim, Hyung-Kyu Lim, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Sang-Bo Lee, Jae-Gwan Park, Jong-Woo Park, Jung-Hwa Lee, Seung-Moon Yoo, Jei-Hwan Yoo, Joungho Kim, Jinman Han, Byung-sik Moon, Kang-yoon Lee, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1635-1644
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an
Autor:
Jong-Woo Park, Chang-Hyun Kim, Jinman Han, Kang-yoon Lee, Jei-Hwan Yoo, Byung-sik Moon, Moon-Hae Son, Joungho Kim, Jae Gwan Park, Ejaz Haq, Keum-Yong Kim, Seung-Moon Yoo, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Hyung-Kyu Lim, Kinam Kim, Bok-Moon Kang, Jung Hwa Lee, Sang-Bo Lee, Kye-Hyun Kyung, Kyu Chan Lee
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible
Autor:
Jei-Hwan Yoo, Chang-Hyun Kim, Kyu-Chan Lee, Kye-Hyun Kyung, Seung-Moon Yoo, Jung-Hwa Lee, Moon-Hae Son, Jin-Man Han, Bok-Moon Kang, Ejaz Haq, Sang-Bo Lee, Jai-Hoon Sim, Joung-Ho Kim, Byung-Sik Moon, Keum-Yong Kim, Jae-Gwan Park, Kyu-Phil Lee, Kang-Yoon Lee, Ki-Nam Kim, Soo-In Cho
Publikováno v:
IEEE Journal of Solid-State Circuits; 1996, Vol. 31 Issue 11, p1635-1644, 10p
Autor:
Jei-Hwan Yoo, Chang Hyun Kim, Kyu Chan Lee, Kye-Hyun Kyung, Seung-Moon Yoo, Jung Hwa Lee, Moon-Hae Son, Jin-Man Han, Bok-Moon Kang, Ejaz Haq, Sang-Bo Lee, Jai-Hoon Sim, Joung-Ho Kim, Byung-Sik Moon, Keum-Yong Kim, Jae Gwan Park, Kyu-Phil Lee, Kang-Yoon Lee, Ki-Nam Kim, Soo-In Cho
Publikováno v:
1996 IEEE International Solid-State Circuits Conference Digest of TEchnical Papers, ISSCC; 1996, p378-379, 2p
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