Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Bok Eng Cheah"'
Publikováno v:
2019 IEEE Asia-Pacific Microwave Conference (APMC).
The proximity effect as well as the roughness of the conductor can increase the conductive loss in differential lines. A trench structure design introduced in [1] has been shown to reduce the negative effects of the proximity effect, however calculat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ef8d16e41f0f1659b0a6a5f7a3d3161
https://doi.org/10.1109/apmc46564.2019.9038191
https://doi.org/10.1109/apmc46564.2019.9038191
Publikováno v:
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC).
The near-end cross talk in high speed single ended bus configuration can have a negative effect of signal integrity. In this work a 3D trench on the reference plane is used to reduce the near-end cross talk in single ended bus. The electromagnetic pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84417144b61e0eae80bfaa98a86b12e0
https://doi.org/10.1109/eptc47984.2019.9026674
https://doi.org/10.1109/eptc47984.2019.9026674
Autor:
Khang Choong Yong, Jackson Chung Peng Kong, Eric Gantner, Stephen H. Hall, Bok Eng Cheah, Chaitanya Sreerama
Publikováno v:
2018 IEEE 20th Electronics Packaging Technology Conference (EPTC).
A high-performance and patent-pending [1] interconnect structure for flex circuits is described in this paper. It is termed Guided Interconnect, as its basic principle is to “guide” the electromagnetic wave of high-speed signaling in a closely-co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5c372acbbce7c016c9d226fa3a1e6709
https://doi.org/10.1109/eptc.2018.8654337
https://doi.org/10.1109/eptc.2018.8654337
Publikováno v:
2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT).
A novel and high-performance interconnect structure is the core of this work. This patent-pending [1] structure is termed Guided Interconnect (GI), as its basic principle is to “guide” the electromagnetic (EM) wave of highspeed signaling in a tig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49d6ada145ec478f78fa4323041f51cc
https://doi.org/10.1109/iemt.2018.8511655
https://doi.org/10.1109/iemt.2018.8511655
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
A novel and patent-pending [1] routing configuration to address the multi-reflection noise caused by the vertical interconnect viz. plated-through-hole (PTH) is presented in this paper. The PTHs are frequently found in any packaging and printed circu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2ee9a8f317d2da6fd7dd03ecb835f29a
https://doi.org/10.1109/eptc.2017.8277440
https://doi.org/10.1109/eptc.2017.8277440
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
This work describes an innovative low-loss transmission line routing configuration, which enables improved channel margin in next-generation high-speed serial buses beyond 10Gbps applications. One such example is SuperSpeed Plus USB a.k.a. USB 3.1 Ge
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1bf3147de95348d306177b1f7ed27e1b
https://doi.org/10.1109/eptc.2016.7861534
https://doi.org/10.1109/eptc.2016.7861534
Autor:
Bok Eng Cheah, H. Louis Lo
Publikováno v:
2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).
This paper investigates and discusses the impact of surface roughness on package insertion loss performance for high-speed applications up-to 50GHz. 3D electrical package with Hurray surface roughness modeling was established and simulated. The inser
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8cbf99d6578d9d37c50a628eb9f48b37
https://doi.org/10.1109/eptc.2015.7412292
https://doi.org/10.1109/eptc.2015.7412292
Publikováno v:
2015 6th Asia Symposium on Quality Electronic Design (ASQED).
Maximum current (Imax) distribution across substrate has been one of the major design factors that govern the electronic package form factor. Particularly on ball grid array (BGA) package design, often times Imax distribution determines the number of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd7963bb5cb7a556381297c5c8834e37
https://doi.org/10.1109/acqed.2015.7274009
https://doi.org/10.1109/acqed.2015.7274009
Publikováno v:
ICCE-TW
This paper evaluates the impact of dielectric loss tangent property on electrical insertion loss performance for both conventional and coreless packaging designs up-to 100Gbps datarate. Coreless package with metal grid array (MGA) second level interc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0131d8990e092a4bad4e8e919c8648b9
https://doi.org/10.1109/icce-tw.2015.7216818
https://doi.org/10.1109/icce-tw.2015.7216818
Publikováno v:
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
This paper describes a novel segmented plated-thra-hole (PTH) structure in flip-chip packaging design to address the current and future high-speed signaling and power integrity problems. The design is capable to resolve the high-frequency coupling fr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a205629711c8517ea98213948d704ec
https://doi.org/10.1109/eptc.2014.7028306
https://doi.org/10.1109/eptc.2014.7028306