Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Bogdan F. Romanescu"'
Publikováno v:
IEEE Micro. 31:109-118
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation systems. Detecting bugs and faults requires a clear specification of correct behavior. A new framework for address translation aware m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0ac8ae7633bcdd5b5adc81a3d1a60de5
https://doi.org/10.1109/mm.2010.99
https://doi.org/10.1109/mm.2010.99
Publikováno v:
ACM SIGARCH Computer Architecture News. 35:45-48
In this paper, we present VariaSim, the publicly available Static Statistical Timing Analysis (SSTA) Tool from Duke University. VariaSim enables researchers to analyze the impact of CMOS process variability on the behavior of circuits and systems.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::670651bd59ce8e9250d9306b61d33e93
https://doi.org/10.1145/1360464.1360465
https://doi.org/10.1145/1360464.1360465
Publikováno v:
ASPLOS
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear specification of correct behavior. To address this need, we develop a framewo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::02d5924298c5eb83652def5552c6356c
https://doi.org/10.1145/1736020.1736057
https://doi.org/10.1145/1736020.1736057
Publikováno v:
HPCA
We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the existing cache coherence protocol. In UNITD coherence protocols, the TLBs participate in the cache coherence protocol just like the instruction an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f29c01d33a1ac44c3166ffcc8267506a
https://doi.org/10.1109/hpca.2010.5416643
https://doi.org/10.1109/hpca.2010.5416643
Autor:
Bogdan F. Romanescu, Daniel J. Sorin
Publikováno v:
PACT
To improve the lifetime performance of a multicore chip with simple cores, we propose the Core Cannibalization Architecture (CCA). A chip with CCA provisions a fraction of the cores as cannibalizable cores (CCs). In the absence of hard faults, the CC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3f3d118190c4cce4bf0b971ea7dbe91
https://doi.org/10.1145/1454115.1454124
https://doi.org/10.1145/1454115.1454124
Publikováno v:
Conf. Computing Frontiers
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components-including registers, functional units, and L1I and L1D cache frames-without slowing the clock frequen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3fe9550a1e8490ccc95c18b070fbb01
https://doi.org/10.1145/1366230.1366257
https://doi.org/10.1145/1366230.1366257