Výsledky vyhledávání - "Blaise Jacquier"

Estimation of Oxide Breakdown Voltage During a CDM Event Using Very Fast Transmission Line Pulse and Transmission Line Pulse Measurements

Autor: Emmanuel Simeu, Jean-Daniel Arnould, Chloe Troussier, Johan Bourgeat, Blaise Jacquier

Publikováno v: IRPS
IEEE International Reliability Physics Symposium (IRPS 2021)
IEEE International Reliability Physics Symposium (IRPS 2021), Mar 2021, Monterey, CA, United States. ⟨10.1109/IRPS46558.2021.9405110⟩

International audience; Using TLP (Transmission Line Pulse) and VF-TLP (Very Fast Transmission Line Pulse) to emulate a fast transient stress, a study of oxide reliability during a CDM (Charged Devise Model) event was done to establish an empirical l

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::93bf64c60bafa2d834721e9062f194d2
https://doi.org/10.1109/irps46558.2021.9405110

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Experimental results on diodes and BIMOS ESD devices in 28 nm FD-SOI under TLP & TID radiation

Autor: F. Soto, Denis Flandre, Ph. Galy, Blaise Jacquier, Valeria Kilchytska, Johan Bourgeat

Publikováno v: Microelectronics Reliability, Vol. 114, p. 113938 (2020)

The electrostatic discharge (ESD) protection is a major concern for advanced CMOS technology manufacturing. Several solutions are available on market with efficient robustness and compliant with the ESD window especially in 28 nm FD-SOI technology. I

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0f4acfa7d2c502c573ed76f9ff8e05c8
https://hdl.handle.net/2078.1/237494

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Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes

Autor: Nicolas Guitard, Philippe Galy, Blaise Jacquier, Bruno Allard, Luong Viet Phung, Jorge Loayza

Publikováno v: Microelectronics Reliability
Microelectronics Reliability, Elsevier, 2018, 85, pp.176-189. ⟨10.1016/j.microrel.2018.04.013⟩

International audience; A new SCR-based device for ESD protection is presented through TCAD simulation and experimental results on a standalone configuration and for a power supply ESD clamp strategy. The new device can turn-off even if the voltage p

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7d5993fcadc5e740f7df0c7daac372dc
https://doi.org/10.1016/j.microrel.2018.04.013

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Intrinsic ESD robustness on new high voltage N/PMOS devices in 28 nm FDSOI UTBB CMOS technology through TLP/VFTLP characterizations

Autor: Blaise Jacquier, Sebastien Haendler, Ph. Galy

Publikováno v: Microelectronics Reliability. 126:114370

The robustness of intrinsic electrostatic discharge (ESD) is a major topic for the fabrication of advanced CMOS technology and in particular for high voltage (HV) N/PMOS transistors. In this study, it is reported the way to fabricate a HV MOS in stan

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8b6644769157a0f7a14feb8731be08f1
https://doi.org/10.1016/j.microrel.2021.114370

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An automated tool for chip-scale ESD network exploration and verification

Autor: Mathieu Fer, Philippe Galy, Blaise Jacquier, Bruno Allard, Benjamin Viale, J. Lescot, Lionel Courau

Publikováno v: 2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

This paper describes a tool for full-chip static ESD (ElectroStatic Discharge) verification called ESD IP Explorer. The tool feasibility is first demonstrated on a 64-pin custom R&D testchip. Its scalability is tested in a second example involving a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e7f7f9e66a8304a1091e71f628d1543c
https://doi.org/10.1109/eosesd.2016.7592551

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Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology

Autor: Ghislain Troussier, Johan Bourgeat, Nicolas Guitard, D. Marin-Cudraz, Jean Jimenez, Alexandre Dray, Philippe Galy, Blaise Jacquier

Publikováno v: Microelectronics Reliability. 52:1998-2004

The purpose of this paper is to present a new trigger design solution to address a double challenge. The first challenge is to trigger a dual back to back SCR during an ESD event with symmetrical response. And the second one is to obtain a pull-up fu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cfc73c4af385c7c1006f95f2561e068b
https://doi.org/10.1016/j.microrel.2012.06.117

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Reliability impact due to high current, lattice and hot carriers temperatures on β(2×2) matrix ESD power devices for advanced CMOS technologies

Autor: Jean Jimenez, D. Marin-Cudraz, Blaise Jacquier, Philippe Galy, Sylvain Dudit, Johan Bourgeat

Publikováno v: Microelectronics Reliability. 51:1608-1613

The main purpose of this paper is to present the behavior of a β (2×2) matrix ESD power device with the effects of high ESD current, lattice and hot carriers temperatures. The beta matrix is a candidate for ESD device network for advanced CMOS tech

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::afef2cae6aa00b593cc0ff02b053d2a9
https://doi.org/10.1016/j.microrel.2011.07.046

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EOS characterization methodology applied to disable feature of ESD power clamps

Autor: Vicky Batra, Luong Viet Phung, Bruno Allard, Divya Agarwal, Nicolas Guitard, Alexandre Dray, Jorge Loayza, Blaise Jacquier

Publikováno v: 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

This work presents an EOS characterization methodology for ESD clamps. BigFET-based and SCR-based power clamps with and without disable feature are characterized. Thanks to the proposed characterization methodology, robustness comparison is provided

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::aaebb81d5cf60c34e94bf4f5102b8484
https://doi.org/10.1109/eosesd.2015.7314782

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Beta-Matrix ESD network: Throughout end of placement rules?

Autor: Blaise Jacquier, Johan Bourgeat, Ph. Galy

Publikováno v: 2011 IEEE International Conference on IC Design & Technology.

Electrostatic Discharge (ESD) protection for advanced CMOS technologies is based on efficient device Network. But these protection strategies imply some constraint on IO and particularly on the frame and the placement in IO ring. In this context we d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::acfc656c972e673b8888aacb6f7c5542
https://doi.org/10.1109/icicdt.2011.5783235

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