Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Bjornar Hernes"'
Publikováno v:
Analog Integrated Circuits and Signal Processing. 62:179-192
High-resolution and very high resolution data conversion is dominated by the use of delta-sigma modulating converters. Oversampling and noise-shaping is employed to enable a coarsely quantized conversion with high effective resolution. The time-domai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e83cbb8f5cd0c373a840492115ddd811
https://doi.org/10.1007/s10470-009-9337-3
https://doi.org/10.1007/s10470-009-9337-3
Autor:
Bjornar Hernes, Frode Telsto, Oystein Moldsvor, J. Bjornsen, T.E. Bonnerud, Atle Briskemyr, Terje Nortvedt Andersen
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:1506-1513
A 12-bit pipeline ADC fabricated in a 0.18-/spl mu/m pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10-MHz input signal with 2V/s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb605ea5a1f57ab7d15054fb151039af
https://doi.org/10.1109/jssc.2005.847519
https://doi.org/10.1109/jssc.2005.847519
Publikováno v:
CICC
A 5th order continuous time delta sigma modulator is designed in 0.18μm CMOS. At a sampling rate of 500MHz it achieves 76dB SNDR over a 10MHz bandwidth consuming 58mW. 5th order noiseshaping is realized with 4 opamp based RC integrators and a VCO re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8700617c2404654d658f5ed27702f3c9
https://doi.org/10.1109/cicc.2013.6658527
https://doi.org/10.1109/cicc.2013.6658527
Autor:
Atle Briskemyr, Oystein Moldsvor, Bjornar Hernes, Thomas E. Bonnerud, Terje Nortvedt Andersen, Frode Telsto, J. Bjornsen
Publikováno v:
DATE
A 12 bit pipeline ADC fabricated in a 0.18 /spl mu/m pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10 MHz input signal with 2V/s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae2b53d9071466506b465c02d9fc08ea
https://doi.org/10.1109/date.2005.3
https://doi.org/10.1109/date.2005.3
Autor:
Oystein Moldsvor, Thomas E. Bonnerud, Terje Nortvedt Andersen, Atle Briskemyr, Bjornar Hernes, J. Bjornsen, Frode Telsto
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference.
A 12 bit pipeline ADC, fabricated in a 0.18 /spl mu/m pure digital CMOS technology, is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10 MHz input signal with 2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06ef864c6334dab67e0f03271dafdb86
https://doi.org/10.1109/esscir.2004.1356664
https://doi.org/10.1109/esscir.2004.1356664
Autor:
Bjørnar Hernes, Trond Sæther
Broadband opamps for multi-channel communication systems have strong demands on linearity performance. When these opamps are integrated in deep sub-micron CMOS technologies, the signal-swing has to occupy a large part of the rather low supply voltage
