Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Biju K. Raveendran"'
Publikováno v:
International Journal of e-Collaboration. 19:1-20
Collaborative research is an opportunity to bring creative minds together and blend multiple disciplines to churn out innovative solutions. In this era of massive social media and information overload, a streamlined process framework with best practi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bd9586bea50bac41cc4abd27453a8f5b
https://doi.org/10.4018/ijec.315782
https://doi.org/10.4018/ijec.315782
Publikováno v:
2022 IEEE 1st International Conference on Data, Decision and Systems (ICDDS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf15d79942b4b3ec4319fba0f9fda1a6
https://doi.org/10.1109/icdds56399.2022.10037556
https://doi.org/10.1109/icdds56399.2022.10037556
Publikováno v:
2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::959d51385969193409733ed26cc75de2
https://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00119
https://doi.org/10.1109/hpcc-dss-smartcity-dependsys53884.2021.00119
Publikováno v:
DS-RT
The tremendous needs of computing power and predictive timing behaviours of modern systems bring revolutionary changes in memory subsystem architecture. One such improvement is the usage of locked caches to have predictive execution time. The existin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f2df38a0a4ec09454d1e5db617d46ae
https://doi.org/10.1109/ds-rt52167.2021.9576135
https://doi.org/10.1109/ds-rt52167.2021.9576135
Publikováno v:
Sustainable Computing: Informatics and Systems. 15:63-81
This paper proposes Leakage Aware Multi-Core Scheduler (LAMCS), an energy efficient mixed task set dynamic voltage and frequency scaling scheduler for multi-core processors. LAMCS schedules mixed task set where hard and soft real-time tasks co-exist.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1630da7eb3c7f071361bee477ec51b07
https://doi.org/10.1016/j.suscom.2017.06.001
https://doi.org/10.1016/j.suscom.2017.06.001
Publikováno v:
VLSI Design
This paper proposes a novel TLB architecture - Deterministic Translation Lookaside Buffer – to reduce TLB misses, energy consumption and effective per access time. DTLB offers tighter upper bound on worst case execution time of real time tasks. Thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4491760f68314bb505f621b564a2588c
https://doi.org/10.1109/vlsid.2017.50
https://doi.org/10.1109/vlsid.2017.50
Publikováno v:
International Journal of Embedded Systems. 11:461
Optimising energy consumption has become the primary focus of research in recent years. Static and dynamic energy optimisation during task scheduling is one of the most prominent measures available. This is achieved mainly by shutdown and slowdown te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60721193bc4f3c1468a64aa406adfedb
https://doi.org/10.1504/ijes.2019.10022126
https://doi.org/10.1504/ijes.2019.10022126
Publikováno v:
International Journal of Embedded Systems. 11:493
This paper proposes a novel cache coherence protocol - MOESIF - to improve the off chip and on chip bandwidth usage. This is achieved by the reducing the number of write backs to the next level memory and by reducing the numbers of responders to a ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bbaff109f53c5b06ddeee6de8bd0b916
https://doi.org/10.1504/ijes.2019.10022129
https://doi.org/10.1504/ijes.2019.10022129
Publikováno v:
2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER).
Cache is one of the most power-consuming components in computer architecture. Power reduction in cache can be achieved by reducing miss rate miss penalty latency per access and power consumption per access. The power reduction can also be achieved by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::134e192255f3b48226052b58819e8d03
https://doi.org/10.1109/discover.2016.7806218
https://doi.org/10.1109/discover.2016.7806218
Publikováno v:
CoDIT
Energy consumption plays an important role in designing embedded devices. In recent years, leakage energy gained significant importance in overall energy consumption. This paper addresses leakage energy at operating system level by optimizing schedul
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d053a755a7a341739e1ce244f9ca3abf
https://doi.org/10.1109/codit.2016.7593575
https://doi.org/10.1109/codit.2016.7593575