Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Bharath Nandakumar"'
Autor:
Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran
Publikováno v:
2022 IEEE International Test Conference (ITC).
Autor:
Bharath Nandakumar, Madhur Maheshwari, Sameer Chillarige, Robert Redburn, Jeff Zimmerman, Nicholai L Esperance, Edward Dziarcak
Publikováno v:
2022 IEEE International Test Conference (ITC).
Publikováno v:
2022 IEEE International Test Conference India (ITC India).
Autor:
Bharath Nandakumar, Robert C. Redburn, Nicholai L' Esperance, Sameer Chillarige, Atul Chabbra, Anil K. Malik
Publikováno v:
ITC
The main goal of existing scan chain diagnosis approaches is to identify a point (or range of points) in the scan chain(s) at which values are directly corrupted due to a defect. A common assumption made in these techniques is the defect causing fail
Autor:
Atul Chabbra, Anil K. Malik, Jeff Zimmerman, Robert C. Redburn, Nicholai L' Esperance, Adisun Wheelock, Sameer Chillarige, Bharath Nandakumar, Martin Amodeo
Publikováno v:
2020 IEEE International Test Conference India.
Numerous areas of VLSI Design and Automation including test and diagnosis have already started benefiting from machine learning based approaches. In this paper, we focus on application of machine learning techniques in the context of Volume Diagnosis
Autor:
Wilson Pradeep, Atul Chhabra, Anil K. Malik, Sameer Chillarige, Bharath Nandakumar, Prakash Narayanan
Publikováno v:
2019 IEEE International Test Conference India (ITC India).
Need for competitive part with reduced cost of build is pushing the boundaries of scan compression adoption in high volume designs. This opens up multiple challenges in effective failure diagnosis, especially in deep sub nanometer designs with higher
Publikováno v:
2019 IEEE International Test Conference India (ITC India).
Traditional software-based scan chain diagnosis methodology requires failures from scan chain shift pattern(s) and a few logic patterns to identify the location of defective flop(s). The number of failures required for this methodology is massively h
Publikováno v:
2013 World Congress on Computer and Information Technology (WCCIT).