Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Bharat M. Pathak"'
Autor:
Ali Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzman, Chang Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, Owen W. Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen V. Prabhu, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, Bharat M. Pathak, Pranav Kalavade
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::177753a2ce8bb9f42c2ea9a8a3d32f41
https://doi.org/10.1109/isscc42615.2023.10067616
https://doi.org/10.1109/isscc42615.2023.10067616
Autor:
Rezaul Haque, Aliasgar S. Madraswala, Cindy Sun, Bharat M. Pathak, Jacqueline Snyder, Kristopher H. Gaewsky, Ali Khakifirooz, Binh Ngo, Chang Wan Ha, Prabhu Naveen Vittal, Karthikeyan Ramamurthi, Fastow Richard, Shantanu R. Rajwade, Owen W. Jungroth, Deepak Thimmegowda, Pranav Kalavade, Rohit S. Shenoy, Steven Law, Sriram Balasubrahmanyam
Publikováno v:
ISSCC
Continued improvement in the 3D NAND bit density is essential to satisfy the exponentially growing demand for data storage. The transition from 3b/cell (TLC) to 4b/cell (QLC) is a significant step towards delivering higher bit density. The increased
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb44bd4a0a1dc88696b6b21df77445d2
https://doi.org/10.1109/isscc42613.2021.9365777
https://doi.org/10.1109/isscc42613.2021.9365777
Autor:
Katie Nguyen, Yasuhiro Takashima, Chris Haid, Martin Szwarc, Vikram Mehta, Owen W. Jungroth, Andy Sendrowski, Hiroyuki Yokoyama, Satoru Tamada, Raymond W. Zeng, Bharat M. Pathak, Matthew Goldman, Tetsuji Manabe, Darshak Udeshi, Ravinder Kajley, Navneet Chalagalla, Tom Ryan, Daniel Elmhurst, Toru Tanzawa, Takaaki Ichikawa, William Sheung, Atif Huq, Mase J. Taub, Joel T. Jorgensen, Yoko Oikawa, Nishant Kajla, Midori Morooka, Tomoharu Tanaka, Koichi Kawai, Jiro Kishimoto, Dan Chu, Shigekazu Yamada, Rod Rozman, Ali Madraswala
Publikováno v:
ISSCC
As applications for NAND continue to grow and cost remains a primary market driver, it is necessary to deliver increased storage capacities at smaller process lithography while meeting high performance requirements [1,2]. Design plays a pivotal role
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae7b73a5ab74e41dd0355efe63091266
https://doi.org/10.1109/isscc.2009.4977395
https://doi.org/10.1109/isscc.2009.4977395
Autor:
R.L. Melcher, Jahanshir J. Javanifard, J.I. Tacata, Peining Wang, Rajesh Sundaram, Priya Walimbe, Bharat M. Pathak
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
Improved performance of flash memories requires programming more cells in parallel. This design uses an inductive pump to transfer the energy to a capacitor to achieve the needed voltage. The discrete inductor is bonded atop the die which also includ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a547996968d2a6c0ec55ffa7fd97ef03
https://doi.org/10.1109/isscc.2005.1493863
https://doi.org/10.1109/isscc.2005.1493863
Autor:
B. Chauhan, R. De Luna, T. Rahman, C. Bueb, T. Ly, N. Chrisman, Matthew Goldman, S. Krishnamachari, Bharat M. Pathak, D. Ward, P. Govindu, M. Khandaker, F. Marvin, K. Fan, T. Bressie, P. Walimbe, Daniel Elmhurst, Rupinder Bains, Q. Nguyen, M. Dayley, P. Lavapie, D.R. Zeng, Balaji Srinivasan, K. Loe, H. Zhang, Saad Monasa, A. Huq, Jerry A. Kreifels, R. Sundaram, E. Carrieri, A. Proescholdt, R.L. Melcher
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
Application of multilevel cell (MLC) technology to a flexible read-while-write flash memory has been achieved through the use of a highly optimized sensing architecture. The goal of this implementation is to provide performance on par with single-bit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ee28e95aca572dc52da2194f8a86895
https://doi.org/10.1109/isscc.2003.1234304
https://doi.org/10.1109/isscc.2003.1234304
Autor:
Saad Monasa, M.I. Ishac, K. Augustine, T. Bressie, S.S. Saini, M. Szwarc, Sriram Balasubrahmanyam, Balaji Srinivasan, Hernan A. Castro, M. Dayley, Raymond W. Zeng, G. Vadlamudi, Christopher John Haid, Daniel Elmhurst, Karthikeyan Ramamurthi, Ahsanur Rahman, K. Loe, R.L. Melcher, S. Chandramouli, J.A. Kreifels, V. Viajedor, R.R. Nambiar, Quan H. Ngo, R. Rajagopal, T. Ly, M. Khandaker, A.T. Sayed, Bo Li, R. Padilla, F. Marvin, K. Fan, G. Christensen, Matthew Goldman, Bharat M. Pathak, I. Sharif, Rezaul Haque
Publikováno v:
2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
We describe the design of a high performance 2 bits per cell flash memory device capable of 8ns synchronous access rate capable of operation at up to 125MHz in burst mode and asynchronous page mode access rate of 14ns. The device is fabricated on Int
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95c5f1b582416407897b2b7bd16530d1
https://doi.org/10.1109/vlsic.2002.1015111
https://doi.org/10.1109/vlsic.2002.1015111
Autor:
Joel T. Jorgensen, T. Ly, Mase J. Taub, D. Pierce, Rajesh Sundaram, Matthew Goldman, R. Kajley, G. Christensen, Saad Monasa, E. Yu, Alec W. Smidt, W. Tran, A. Sendrowski, Rezaul Haque, Bharat M. Pathak, A. Darwish, Q. Nguyen, Priya Walimbe, A. Cabrera, I. Sharif, R. Trivedi, F. Marvin, H. Shimoyoshi
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
A flash memory with flexible multi-partition architecture allows programming or erasing in one partition while reading from another partition. The 64 Mb memory uses a 0.18 /spl mu/m process that has a 0.32 /spl mu/m/sup 2/ cell. The device has 18 ns
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66818fc9f311b1559d8359e73c6e9a02
https://doi.org/10.1109/isscc.2001.912420
https://doi.org/10.1109/isscc.2001.912420