Variance Analysis in 3D Integration: A statistically Unified Model with Distance Correlations

Autor: Perrine Batude, Alexandre Ayres, Laurent Brunet, Olivier Rozeau, Maud Vinet, Bertrand Borot, Laurent Fesquet

Publikováno v: IEEE Transactions on Electron Devices
IEEE Transactions on Electron Devices, Institute of Electrical and Electronics Engineers, 2019, 66 (1), pp.633-640. ⟨10.1109/TED.2018.2879680⟩
IEEE Transactions on Electron Devices, 2019, 66 (1), pp.633-640. ⟨10.1109/TED.2018.2879680⟩

International audience; Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netli

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::91e7e64e098cf2e959536ff1d2ba415c
https://hal.archives-ouvertes.fr/hal-01971015

Using Model for Assessment of Complementary Metal Oxide Semiconductor Technology and Roadmaps as a Pre-Simulation Program with Integrated Circuit Emphasis Model Generator for Early Technology and Circuit Simulation

Autor: Frederic Boeuf, Manuel Sellier, Thomas Skotnicki, Bertrand Borot, F. Payet

Publikováno v: Japanese Journal of Applied Physics. 47:3384-3389

In this work, we show how to use the model for assessment of CMOS technology and roadmaps (MASTAR) in order to generate ready-to-use simple pre-simulation program with integrated circuit emphasis (pre-SPICE) data. Calibration of MASTAR on silicon dat

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::04dd928f1ca0bf495449f0211bdc1d6c
https://doi.org/10.1143/jjap.47.3384

Test structures for interdie variations monitoring in presence of statistical random variability

Autor: Dominique Golanski, David Hoguet, Bertrand Borot, Jean-Michel Portal, Giancarlo Castaneda, Gerard Ghibaudo, Andre Juge

Publikováno v: 2012 IEEE International Conference on Microelectronic Test Structures.

We study the limitations of single transistor test structures for Process Variations monitoring in presence of statistical random variability, and compare them with transistor array structures in 45 CMOS technology. By optimizing transistor array des

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::76a1e399ae52583780113da6117aeb95
https://doi.org/10.1109/icmts.2012.6190609

Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm

Autor: Lionel Thevenon, Jean Damien Chapon, Marianne Decaux, Mark Joyner, Avi Cohen, Nicolas Cluet, Fabrice Baron, Bertrand Borot, Frank Sundermann, Erez Graitzer, K. Dabertrand, Bertrand Le Gratiet, Yoann Blancquaert, Raphael Bingert, Pascal Gourard, Alain Ostrovsky, Laurene Babaud, Benedicte Bry, C. Monget, Ute Buttgereit, Jean Massin, Robert Birkner, Thierry Devoivre, Nicolas Thivolle

Publikováno v: SPIE Proceedings.

Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to reduce CD dispersion. After a global CD budget evaluation at SPIE08 [1], we have been focusing on Intrafield CD corrections using Dose Mapper™[2].

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d3b3cfd42306ebd56a82512b0952db53
https://doi.org/10.1117/12.845987

Mixed test structure for soft and hard defect detection

Autor: Bertrand Borot, Hassen Aziza, J.-M. Portal, F. Rigaud, Fabrice Argoud, J. Vast, D. Nee

Publikováno v: 2008 IEEE International Conference on Microelectronic Test Structures.

The objective of this paper is to present a mixed test structure designed to characterize yield losses due to hard defect and back-end process variation (PV) at die and wafer level. A brief overview of the structure, designed in a ST-Microelectronics

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0f5ec19f831d5410658ec5a09957b80a
https://doi.org/10.1109/icmts.2008.4509313