Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Bernd Wuppermann"'
Autor:
Robert M. R. Neff, Bernd Wuppermann, Charles Wu, Dusan Stepanovic, N.J. Guilar, Cheongyuen W. Tsang, John Keane, Ken Nishimura
Publikováno v:
ISSCC
This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5d99612fb0f58bcd0e4305faa650de7
https://doi.org/10.1109/isscc.2017.7870372
https://doi.org/10.1109/isscc.2017.7870372
Autor:
V. Abramzon, R. Pasha, M. Martin, S. Ray, A. Al-Adnani, Peter Brandt, Brian D. Setterberg, D. J. Huber, Kenneth D. Poulton, Annemie Jacobs, Gunter Steinbach, M. Clayson, John Patrick Keane, Bernd Wuppermann, E. Peeters, F. Demarsin
Publikováno v:
ISSCC
Metastable events in ADC comparators cause large errors that cannot be tolerated in test and measurement applications that record data over extended time intervals. This work utilizes BiCMOS technology to provide high dynamic range analog-to-digital
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c961d9cee255d55d82bf6d43de41b63
https://doi.org/10.1109/isscc.2013.6487817
https://doi.org/10.1109/isscc.2013.6487817
Publikováno v:
2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).
A dual-path PLL comprising two LC VCOs covers a tuning range from 8.2 to 20.1 GHz. Able to operate with a wide range of feedback-divider ratios (N), the PLL provides a total jitter of 65.3 fsrms when N=2 and 206.1 fsrms when N=16. In addition, the PL
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::996b6230cef04cf8942b48974a71097c
https://doi.org/10.1109/csics.2010.5619666
https://doi.org/10.1109/csics.2010.5619666
Publikováno v:
Analog Circuit Design ISBN: 9781402051852
Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba44c01a73f4ca25ecf6ea1aa8abf7bb
https://doi.org/10.1007/1-4020-5186-7_2
https://doi.org/10.1007/1-4020-5186-7_2
Autor:
R. Jewett, Bernd Wuppermann, T. Kopley, C. Tan, J. Pernillo, Robert M. R. Neff, Brian D. Setterberg, A. Montijo, Kenneth D. Poulton
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
A 20 GS/s 8-bit ADC achieves a bandwidth of 6 GHz in 0.18 /spl mu/m CMOS. The implementation uses 80 time-interleaved current-mode pipeline sub-ADCs and stores data at 20 GB/s into a 1 MB on-chip memory. The ADC is packaged with a BiCMOS input buffer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8bb82fc6a66efba3b41da99c73744264
https://doi.org/10.1109/isscc.2003.1234315
https://doi.org/10.1109/isscc.2003.1234315
Conference
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