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Autor:
Benoit Ganne, Patrice Couvert, Renaud Ayrignac, Benoît Dupont de Dinechin, Samuel Jones, Frederic Riss, Thierry Strudel, Nicolas Morey Chaisemartin, Francois Jacquet, Pierre Guironnet de Massas, Pierre-Edouard Beaucamps
Publikováno v:
HPEC
The Kalray MPPA-256 processor integrates 256 user cores and 32 system cores on a chip with 28nm CMOS technology. Each core implements a 32-bit 5-issue VLIW architecture. These cores are distributed across 16 compute clusters of 16+1 cores, and 4 quad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9ea33daf47010fa4906055b7dd165360
https://doi.org/10.1109/hpec.2013.6670342
https://doi.org/10.1109/hpec.2013.6670342
