A Qualitative Approach to Many‐core Architecture

Autor: Benoît Dupont de Dinechin

Publikováno v: Multi-Processor System-on-Chip 1

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6ae58f5c6cf07372c810fc9b7b5d56f3
https://doi.org/10.1002/9781119818298.ch2

Distortion Approximation of a Compressed Softmax Layer

Autor: Diana Resmerita, Rodrigo Cabral Farias, Lionel Fillatre, Benoît Dupont de Dinechin

Publikováno v: SSP

Deep neural networks need to be compressed due to their high memory requirements and computational complexity. Numerous compression methods have been proposed to solve this issue, but we still do not fully understand how the compression error will im

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::882a55e8f2be6db6a45215f123891454
https://doi.org/10.1109/ssp49050.2021.9513733

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

Autor: Marc Boyer, Jörn Migge, Amaury Graillat, Benoît Dupont de Dinechin

Publikováno v: Performance Evaluation
Performance Evaluation, Elsevier, 2020, 143, pp.102124. ⟨10.1016/j.peva.2020.102124⟩

International audience; The Kalray MPPA2-256 processor integrates 256 processing cores and 32 management cores on a chip. These cores are grouped into clusters and clusters are connected by a high-performance network on chip (NoC). This NoC provides

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4314edfd3d90058670be399da8eca577
https://hal.archives-ouvertes.fr/hal-03170466/document

Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip

Autor: Matthieu Moy, Claire Maiza, Benoît Dupont de Dinechin, Pascal Raymond, Amaury Graillat

Publikováno v: RTNS 2019-27th International Conference on Real-Time Networks and Systems
RTNS 2019-27th International Conference on Real-Time Networks and Systems, Nov 2019, Toulouse, France. pp.61-69, ⟨10.1145/3356401.3356416⟩
RTNS

We consider hard real-time applications running on many-core processor containing several clusters of cores linked by a Network-on-Chip (NoC). Communications are done via shared memory within a cluster and through the NoC for inter-cluster communicat

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::487430f9c8f95d2967ed441ebd1910d4
https://hal.science/hal-02320463/file/rtns2019.pdf

Parallel Code Generation of Synchronous Programs for a Many-core Architecture

Autor: Pascal Raymond, Matthieu Moy, Benoît Dupont de Dinechin, Amaury Graillat

Publikováno v: DATE 2018-Design, Automation and Test in Europe
DATE 2018-Design, Automation and Test in Europe, Mar 2018, Dresden, Germany. pp.1139-1142, ⟨10.23919/DATE.2018.8342182⟩
DATE

International audience; Embedded systems tend to require more and more computational power. Many-core architectures are good candidates since they offer power and are considered more time predictable than classical multi-cores. Data-flow Synchronous

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::850e4a8b3dff02107fa20c63280f7a11
https://hal.inria.fr/hal-01667594