Výsledky vyhledávání - "Benjamin S. Devlin"

Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs

Autor: Ilya K. Ganusov, Benjamin S. Devlin

Publikováno v: FPL

This paper presents enhancements to the Xilinx UltraScale+ clocking architecture to support fine-grain time-borrowing. Time borrowing improves performance by redistributing timing slack between fast and slow paths. The Ultra-Scale+ architecture intro

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2030b8fc2dfd4f7c853afbe7e5e422c3
https://doi.org/10.1109/fpl.2016.7577343

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A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation

Autor: Benjamin S. Devlin, Makoto Ikeda, Kunihiro Asada

Publikováno v: IEEE Journal of Solid-State Circuits. 46:2500-2513

A 65 nm self-synchronous field programmable gate array (SSFPGA) with delay insensitive operation and pipeline granularity at the gate level, is shown to be robust to process voltage and temperature (PVT) variations. The proposed SSFPGA employs a 38 �

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::45e8cd73d8a799fc9a51f6f80c5e7e86
https://doi.org/10.1109/jssc.2011.2164024

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A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment

Autor: Makoto Ikeda, Kunihiro Asada, Benjamin S. Devlin, Toru Nakura

Publikováno v: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1319-1328

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A se

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a45e9b49a6b8b5a0688b10b3747664ba
https://doi.org/10.1587/transfun.e93.a.1319

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Completely self-synchronous 1024-bit RSA crypt-engine in 40nm CMOS

Autor: Kazuhiko Fukushima, Benjamin S. Devlin, Makoto Ikeda, Hiroshi Ueki

Publikováno v: 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

We have designed and measured completely self-synchronous 1024-bit RSA crypt-engine, fabricated in 40nm CMOS. We have implemented two modular exponentiation algorithms, the high-to-low(HTL) and Montgomery power ladder(MPL) in order to show the perfor

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::55a441a5a0ad3ab5e891d16d665bca48
https://doi.org/10.1109/asscc.2013.6691044

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Performance and side-channel attack analysis of a self synchronous montgomery multiplier processing element for RSA in 40nm CMOS

Autor: Makoto Ikeda, Benjamin S. Devlin, Kunihiro Asada, Shintaro Mori, Shigenori Miyauchi, Hiroshi Ueki

Publikováno v: 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

We propose a Montgomery multiplier composed of gate-level self synchronous processing elements (SS-PE) that can be used to create scalable-length modular multipliers with no broadcast signals for high throughput. A 40nm test circuit shows the SS-PE o

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a6abce849d7f633d5670e89b64ff03b0
https://doi.org/10.1109/asscc.2012.6570807

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Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system

Autor: Kunihiro Asada, Benjamin S. Devlin, Makoto Ikeda

Publikováno v: ICECS

In this paper we present an autonomous watchdog circuit for error robustness which can detect logic errors caused by power supply noises and soft errors, with the smallest overheads compared to current research. The proposed watchdog circuit is reali

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1766555012e9de7fbaf017f308d1d881
https://doi.org/10.1109/icecs.2011.6122212

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A 65nm 2.97GHz self Synchronous FPGA with 42% power bounce tolerance

Autor: Kunihiro Asada, Benjamin S. Devlin, Makoto Ikeda

Publikováno v: 2010 IEEE Asian Solid-State Circuits Conference.

The performance and robustness to PVT variations has been measured of an improved Self Synchronous FPGA (SSFPGA) designed in 65nm CMOS which achieves 2.97GHz throughput at 1.2V. The proposed SSFPGA employs a 38×38 array of 4-input, 3-stage Self Sync

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::45af6d69095a0f429752c0551066da6e
https://doi.org/10.1109/asscc.2010.5716572

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Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging

Autor: T. Sogabe, Makoto Ikeda, Benjamin S. Devlin, Kunihiro Asada

Publikováno v: DFT

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9c9cb33adba7c8758c1e9bc34c582a61
https://doi.org/10.1109/dft.2010.61

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Evaluation on the reliable operation of a Gate-Level Pipelined Self Synchronous system against PVT and aging

Autor: Benjamin S. Devlin, Kunihiro Asada, Makoto Ikeda

Publikováno v: 2010 IEEE International Integrated Reliability Workshop Final Report.

The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage S

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::70259de9f55b7b87cb12ef0e33fe4f02
https://doi.org/10.1109/iirw.2010.5706500

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