Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Benjamin Duclaux"'
Autor:
Benjamin Duclaux, Maxime Gatefait, Alice Pelletier, Laurent Lecarpentier, Pierre Leveque, Cedric Monget
Publikováno v:
Metrology, Inspection, and Process Control XXXVII.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b42a1a88b1c67495ff393c25e968ba69
https://doi.org/10.1117/12.2655762
https://doi.org/10.1117/12.2655762
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXIV.
As the industry moves from node to node, lithographers have been pushed to use complex models to correct overlay errors and drive down model residuals. High order models are now used in combination with Correction per Exposure capabilities for critic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad9680bdb22bbf291e9c8253bfa6938a
https://doi.org/10.1117/12.2551062
https://doi.org/10.1117/12.2551062
Autor:
B. Le-Gratiet, Maxime Gatefait, Didier Dabernat, Olivier Mermet, Benjamin Duclaux, Florent Dettoni
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXIV.
Advanced nodes require tighter and tighter overlay control to secure products yield. Market like automotive one are even more demanding on “overlay reliability” till the extreme edge of wafers. High order models including Correction per Exposure
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::516f14314f87cd9b7740561f1a77796e
https://doi.org/10.1117/12.2548308
https://doi.org/10.1117/12.2548308
Autor:
C. Monget, J. Decaunes, Bruno Perrin, Laurene Babaud, Olivier Fagart, Maxime Gatefait, Nicolas Thivolle, Mathieu Guerabsi, Jean-Damien Chapon, Robin Perrier, Alice Pelletier, Benjamin Duclaux
Publikováno v:
2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
I.IntroductionWith overlay requirements getting more and more critical, a lot of work has been done in the industry to improve the overlay correction capability by using high order process corrections, corrections per exposure and heating control (le
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28c8c51f4747c3aebf113d0dd883746d
https://doi.org/10.1109/asmc.2019.8791771
https://doi.org/10.1109/asmc.2019.8791771
Autor:
Neal Lafferty, Hosadurga Shobha, Wenhui Wang, Terry A. Spooner, Tae-Soo Kim, Matthew E. Colburn, Yann Mignot, Yongan Xu, Yunpeng Yin, Benjamin Duclaux, Shyng-Tsong Chen, Chiew-seng Koay, Marcy Beard, James J. Kelly, Oscar van der Straten, Seowoo Nam, Ming He, Nicole Saulnier
Publikováno v:
2013 IEEE International Interconnect Technology Conference - IITC.
For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39a5d247773726f8e5f9ada178ac4257
https://doi.org/10.1109/iitc.2013.6615589
https://doi.org/10.1109/iitc.2013.6615589