Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Benedicte Illescas, Pedro"'
Autor:
Alcaide Portet, Sergi, Cabo Pitarch, Guillem, Bas Jalón, Francisco, Benedicte Illescas, Pedro, Mazzocchetti, Fabio, Cazorla Almeida, Francisco Javier, Abella Ferrer, Jaume
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
The lack of sufficient hardware support for functional safety precludes the full adoption of many Commercial Off-the-Shelf (COTS) MPSoCs in safety-related systems, such as those in the aerospace industry. Some recent MPSoCs come along with programmab
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::e719af64639af2d0b9d337fab890f841
http://hdl.handle.net/2117/370186
http://hdl.handle.net/2117/370186
Autor:
Mazzocchetti, Fabio, Alcaide Portet, Sergi, Bas Jalón, Francisco, Benedicte Illescas, Pedro, Cabo Pitarch, Guillem, Chang, Feng, Fuentes Díaz, Francisco Javier, Abella Ferrer, Jaume
Applications with safety requirements have become ubiquitous nowadays and can be found in edge devices of all kinds. However, microcontrollers in those devices, despite offering moderate performance by implementing multicores and cache hierarchies, m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2cfe2e379098c4cce3bf1669270cf5e
Autor:
Benedicte Illescas, Pedro|||0000-0003-1670-7783, Hernández Gañán, Carlos, Abella Ferrer, Jaume|||0000-0001-7951-4028, Cazorla Almeida, Francisco Javier
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Universitat Politècnica de Catalunya (UPC)
Enabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic timing analysis (MBPTA) tec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::dfe943b4d04bf8155cec0169beeebe11
https://hdl.handle.net/2117/124984
https://hdl.handle.net/2117/124984
Autor:
Benedicte Illescas, Pedro|||0000-0003-1670-7783, Hernandez, C., Abella Ferrer, Jaume|||0000-0001-7951-4028, Cazorla Almeida, Francisco Javier
Publikováno v:
29th International Conference on Probabilistic, Combinatorial and Asymptotic Methods for the Analysis of Algorithms
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and automotive already featurin
Autor:
Benedicte Illescas, Pedro
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
[CATALÀ] Aquest projecte consisteix a analitzar diferents aspectes de la jerarquia de memòria i entendre la seva influència al rendiment del sistema. Els aspectes que s'analitzaran són els algorismes de reemplaçament, els esquemes de mapeig de m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::dc557cf5b944e99d8a5dcf43553616f8
http://hdl.handle.net/2099.1/23771
http://hdl.handle.net/2099.1/23771
Autor:
Bas Jalón, Francisco, Benedicte Illescas, Pedro, Alcaide Portet, Sergi, Cabo Pitarch, Guillem, Mazzocchetti, Fabio, Abella Ferrer, Jaume
Publikováno v:
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Computing systems in the safety domain, such as those in avionics or space, require specific safety measures related to the criticality of the deployment. A problem these systems face is that of transient failures in hardware. A solution commonly use
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::523922a2a545f69cf130bd17a4d568cc
Autor:
Cabo Pitarch, Guillem, Alcaide Portet, Sergi, Hernández Luz, Carles, Benedicte Illescas, Pedro, Bas Jalón, Francisco, Mazzocchetti, Fabio, Abella Ferrer, Jaume
Publikováno v:
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Advanced statistics units (SUs) have been proven effective for the verification, validation and implementation of safety measures as part of safety-related MPSoCs. This is the case, for instance, of the RISC-V MPSoC by CAES Gaisler based on NOEL-V co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9a7da6f039efef1703ee960f3e9c44ec
Autor:
Benedicte Illescas, Pedro
Publikováno v:
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Time Randomised caches (TRc), which can be implemented at hardware level or with software means on conventional deterministic cache designs, have been proposed for real-time systems as key enablers for Probabilistic Timing Analysis (PTA) and in parti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::8c5880cee30addbcef74f87e0847ef0c
http://hdl.handle.net/2117/105978
http://hdl.handle.net/2117/105978