Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Bendik Kleveland"'
Autor:
Ming Liu, Jeff Kumala, Jay M. Patel, Dipak K. Sikdar, Socrates D. Vamvakos, Michael J. Miller, Jayaprakash Balachandran, Ronald B. David, Rajesh Chopra, Mike Morrison, Bendik Kleveland
Publikováno v:
IEEE Micro. 33:56-65
Memory access rate is a primary performance bottleneck in high-performance networking systems. The MoSys Bandwidth Engine family of integrated circuits provides a significant improvement in effective memory performance by using high-speed serial I/O'
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31e0117f1f585662076f6d5fcf2d5e5c
https://doi.org/10.1109/mm.2013.7
https://doi.org/10.1109/mm.2013.7
Autor:
Alvin Wang, Khaldoon Abugharbieh, Claude R. Gauthier, Bendik Kleveland, Shaishav Desai, Socrates D. Vamvakos, Ritesh Saraf, Mahmud Hassan, Jason Yeung, Richard Rouse, Gurupada Mandal, K. C. Hsieh, Sanjay Dabral, Ying Cao, Prashant Choudhary, Chethan Rao, Karthisha Canagasaby
Publikováno v:
Analog Integrated Circuits and Signal Processing. 78:259-273
This paper presents the design and Silicon verification of a 2.488---11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eda7a109416d594abfeecdf1a3af8a0
https://doi.org/10.1007/s10470-013-0172-1
https://doi.org/10.1007/s10470-013-0172-1
Autor:
Luca G. Fasoli, Bendik Kleveland, Ali Al-Shamma, M. Johnson, Quang Nguyen, Derek J. Bosch, Matthew P. Crowley, Tz-yi Liu, Tyler J. Thorp, Thomas H. Lee, M. Farmwald, Roy E. Scheuerlein, Kenneth K. So, Alper Ilkbahar
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1920-1928
A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06ab6d49abbdcec343e1993dcb3f7262
https://doi.org/10.1109/jssc.2003.818147
https://doi.org/10.1109/jssc.2003.818147
Autor:
Jeff Kumala, Ashish Dixit, Pascal Adam, Jay Patel, Sinan Doluca, Ming Liu, Wesley Yu, Anju Tsao, Daniel Yau, Ben Lee, Rajesh Chopra, Jianguang Wang, Mark Hendrickson, Antonio Cruz, Jeong Choi, Byeong Cheol Na, Clement Szeto, Dipak K. Sikdar, Bendik Kleveland, Michael Sporer, Ronald B. David, Mike Morrison, Patrick Chen, Michael J. Miller
Publikováno v:
VLSIC
We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::439eeb93051dcf748484e61739ce0bf4
https://doi.org/10.1109/vlsic.2014.6858414
https://doi.org/10.1109/vlsic.2014.6858414
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1480-1488
The increasing number of interconnect layers that are needed in a CMOS process to meet the routing and power requirements of large digital circuits also yield significant advantages for analog applications. The reverse thickness scaling of the top me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d978607cc9fc2a20043f16e29edfa68
https://doi.org/10.1109/4.953476
https://doi.org/10.1109/4.953476
Autor:
Khaldoon Abugharbieh, Chethan Rao, Sanjay Dabral, Richard Rouse, Alvin Wang, Prashant Choudhary, Karthisha Canagasaby, Gurupada Mandal, Bendik Kleveland, K. C. Hsieh, Ritesh Saraf, Ying Cao, Mahmud Hassan, Claude R. Gauthier, Jason Yeung, Socrates D. Vamvakos, Shaishav Desai
Publikováno v:
MWSCAS
The paper presents the design of a 2.488 – 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d84e261a54381fb88dd2548774b066c
https://doi.org/10.1109/mwscas.2012.6291943
https://doi.org/10.1109/mwscas.2012.6291943
Publikováno v:
IEEE Electron Device Letters. 21:390-392
Conventional ESD guidelines dictate a large protection device close to the pad. The resulting capacitive load causes a severe impedance mismatch and bandwidth degradation. A distributed ESD protection scheme is proposed to enable a low-loss impedance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2554445d43346ebb29426e33a0432df
https://doi.org/10.1109/55.852960
https://doi.org/10.1109/55.852960
Publikováno v:
Solid-State Electronics. 33:743-752
A new spectroscopic method, based on the second derivative of the carrier concentrations vs temperature, is proposed for analyzing van der Pauw-Hall-effect experiments. The validity and merits of the method are illustrated by applying it to simulated
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0fbf6f95f6b53d5f20e9de03a21f06b2
https://doi.org/10.1016/0038-1101(90)90188-k
https://doi.org/10.1016/0038-1101(90)90188-k
Autor:
Bendik Kleveland, Derek J. Bosch, Thomas H. Lee, Tyler J. Thorp, M. Farmwald, Luca G. Fasoli, M. Johnson, Roy E. Scheuerlein, Quang Nguyen, Ali Al-Shamma, Tz-yi Liu, Alper Ilkbahar, Kenneth K. So, Matthew P. Crowley
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
A 3.3 V, 512 Mb PROM uses a transistorless memory cell containing an antifuse and diode. A bit area of 1.4F/sup 2/ including all overhead is achieved by stacking cells 8 high above the 0.25 /spl mu/m CMOS substrate. Read bandwidth is 1 MB/s and write
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fa6f908f93a86fa5caeafd22e568ed6
https://doi.org/10.1109/isscc.2003.1234303
https://doi.org/10.1109/isscc.2003.1234303
Publikováno v:
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
A realistic power grid and pseudo-random signal lines connected to on-chip drivers are included for accurate extraction of the parasitic inductance in a 5-metal layer 0.25-/spl mu/m CMOS technology. A new ring oscillator for the extraction of signal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::267052e36327f909424669b6f4cbebaa
https://doi.org/10.1109/iedm.1999.824294
https://doi.org/10.1109/iedm.1999.824294