Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Belliappa Manavattira Kuttanna"'
Autor:
J. Golab, K.R. Kishore, P. Voldstad, J. Slaton, D. Ogden, Mydung Pham, Christopher Hans Olson, Lee Evan Eisen, Russell Adley Reininger, J. Prado, Michael Clay Alexander, Y.-W. Ho, B. Burgess, P. Ippolito, Robert Thaddeus Golla, R. Harris, S.P. Litch, S.-H. Park, Soummya Mallick, M. Schiffli, Tai Ngo, C. Hunter, Belliappa Manavattira Kuttanna, B. Goins, Romesh Mangho Jessani, S. Reeve, Cang Tran, B. Ho, Carl D. Dietz, Arturo L. Arizpe, J. Eno, J. Kahle, S. Gary, K. Torku, H. Sanchez, R. El-Kareh, K. Hoover, G. Gerosa, D. Pham, G. Thuraisingham, Rajesh Bhikhubhai Patel, N. Vanderschaaf
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
This superscalar microprocessor is a 32b implementation of the PowerPC Architecture. With an estimated performance/power ratio of 25SPECint92/W at 80 MHz, this RISC style chip offers workstation-level performance packed into a low-power consumption,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edf86b993938dd11fde26f303723e7ed
https://doi.org/10.1109/isscc.1994.344665
https://doi.org/10.1109/isscc.1994.344665
Autor:
E. Cheesebrough, Tai Ngo, Soummya Mallick, R. Chitturi, Belliappa Manavattira Kuttanna, Cang Tran, Lee Evan Eisen, Mark D. Sweet, B. Ho, Quan Nguyen, D. Pham, A. Piejko, T. Lyon, Rajesh Bhikhubhai Patel, K. Hoover, Albert J. Loper, Michael Putrino, D. Ogden, J. Kahle, Hung Hua
Publikováno v:
Proceedings ISSCC '95 - International Solid-State Circuits Conference.
This 32 b superscalar processor, having 18 mW/MHz projected power consumption at 66 MHz, is designed for desktop companions and high-end embedded multimedia applications with graphics-intensive requirements such as high-performance video games. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15b7b0a859f102780e9b1481dff3118e
https://doi.org/10.1109/isscc.1995.535513
https://doi.org/10.1109/isscc.1995.535513