Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Belliappa Kuttanna"'
Autor:
Sreenivas Subramoney, Shankar Balachandran, Rahul Bera, Joydeep Rakshit, Anant V. Nori, Avishaii Abuhatzera, Belliappa Kuttanna, Omer Om J
Publikováno v:
ISCA
Deep Neural Networks (DNN) are used in a variety of applications and services. With the evolving nature of DNNs, the race to build optimal hardware (both in datacenter and edge) continues. General purpose multi-core CPUs offer unique attractive advan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b70cc6fafe6f74767e88a660abaa8a6
https://doi.org/10.1109/isca52012.2021.00022
https://doi.org/10.1109/isca52012.2021.00022
Autor:
Sreenivas Subramoney, Hong Wang, Belliappa Kuttanna, Eagle Jones, Jim Radford, Gopi Neela, Biji George, Srivatsava Jandhyala, Omer Om J, Dipan Kumar Mandal, Kalsi Gurpreet S, Santhosh Kumar Rethinagiri, Lance Hacking
Publikováno v:
DATE
Visual Inertial Odometry (VIO) is used for estimating pose and trajectory of a system and is a foundational requirement in many emerging applications like AR/VR, autonomous navigation in cars, drones and robots. In this paper, we analyze key compute
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b2e7c25b90e3e4cdb5645df8742f798
https://doi.org/10.23919/date.2019.8714921
https://doi.org/10.23919/date.2019.8714921
Autor:
Yi-Feng Liu, Joannes G. van de Groenendaal, Ian M. Steiner, Erik A. McShane, Bradley Burres, Praveen Mosur, Sin S. Tan, Sridhar Lakshmanamurthy, Belliappa Kuttanna, Jonathan Robinson
Publikováno v:
IEEE Micro. 35:26-34
The Intel Atom C2000 Microserver, codenamed Avoton and Rangeley, is a complete server and embedded processor system on chip (SoC) that provides up to seven times greater performance and six times the energy efficiency versus the prior-generation proc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f615e20a28b876979c1487996b6257e6
https://doi.org/10.1109/mm.2015.14
https://doi.org/10.1109/mm.2015.14
Autor:
M. D'Addeo, G. Gerosa, H. Samarchi, Belliappa Kuttanna, Binta M. Patel, M.H. Taufique, Bo Jiang, Steve Curtis, F. Merchant
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:73-82
This paper describes a low power Intel Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) with performance similar to mainstream Ultra-Mobile PCs. The design relies on high residency in a new low-power state in order
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b87db0727cfb10ff29a172a67eac9161
https://doi.org/10.1109/jssc.2008.2007170
https://doi.org/10.1109/jssc.2008.2007170
Autor:
Thomas Hartin, Belliappa Kuttanna, Christopher T. Weaver, Guilherme Ottoni, Jason W. Brandt, Hong Wang
Publikováno v:
Conf. Computing Frontiers
Dynamic binary translation (DBT) has been widely used as a means to run applications created for one instruction-set architecture (ISA) on top of processors with a different ISA. Given the great amount of legacy software developed for PCs, based on t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bdb35a771061705e741e35870ebc4429
https://doi.org/10.1145/2016604.2016635
https://doi.org/10.1145/2016604.2016635
Autor:
M.H. Taufique, Bo Jiang, Belliappa Kuttanna, M. D'Addeo, F. Merchant, Binta M. Patel, H. Samarchi, S. Curtis, G. Gerosa
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a628de8bd6d1e2d566ac05c437a4f881
https://doi.org/10.1109/asscc.2008.4708718
https://doi.org/10.1109/asscc.2008.4708718
Autor:
M.H. Taufique, Binta M. Patel, Belliappa Kuttanna, M. D'Addeo, Bo Jiang, H. Samarchi, S. Curtis, F. Merchant, G. Gerosa
Publikováno v:
ISSCC
This paper describes a low-power Intel* Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) and Ultra- Mobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark'05 OP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c9cbdd84606754395d439f6a2e8e7db
https://doi.org/10.1109/isscc.2008.4523154
https://doi.org/10.1109/isscc.2008.4523154