A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs

Autor: Behzad Zeinali, Jens Kargaard Madsen, Farshad Moradi, Praveen Raghavan

Publikováno v: Zeinali, B, Madsen, J K, Raghavan, P & Moradi, F 2019, ' A Novel Nondestructive Bit-Line Discharging Scheme for Deep Submicrometer STT-RAMs ', IEEE Transactions on Emerging Topics in Computing, vol. 7, no. 2, 7744549, pp. 294-300 . https://doi.org/10.1109/TETC.2016.2629090

A combination of semiconductor integrated circuits (IC) and a dense array of scaled magnetic tunnel junctions (MTJ) makes promising Spin-Transfer Torque Random Access Memory (STT-RAM). This emerging memory minimizes the leakage power consumption and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ba469b270edb9c97d8397df6a288138f
https://doi.org/10.1109/tetc.2016.2629090

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology

Autor: Praveen Raghavan, Farshad Moradi, Behzad Zeinali, Jens Kargaard Madsen

Publikováno v: International Journal of Circuit Theory and Applications. 45:1647-1659

Summary A novel sub-threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14-nm FinFET technology is proposed in this paper. The proposed 9 T-SRAM cell offers an improved access time in comparison to the 8 T-SRAM cell. Furth

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d66e2825d02abc47dd21277516449a4c
https://doi.org/10.1002/cta.2280

Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching

Autor: Jens Kargaard Madsen, Farshad Moradi, Behzad Zeinali, Praveen Raghavan

Publikováno v: Zeinali, B, Madsen, J K, Raghavan, P & Moradi, F 2017, Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching . in Proceedings of the IEEE 35th International Conference on Computer Design : ICCD 2017 . IEEE, pp. 463-468, Boston, United States, 05/11/2017 . https://doi.org/10.1109/ICCD.2017.81
ICCD

This paper presents a spin-orbit torque magnetic random access memory (SOT-MRAM) using perpendicular-anisotropy magnetic tunnel junction (p-MTJ). In spite of conventional p-MTJ based SOT-MRAMs which need an external magnetic field to achieve a determ

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::24437623b99355d8584fdb70693f5aa8
https://pure.au.dk/portal/da/publications/ultrafast-sotmram-cell-with-stt-current-for-deterministic-switching(2465414a-c529-44b6-8103-35aefe84d4d4).html

Multilevel SOT-MRAM Cell with a Novel Sensing Scheme for High-Density Memory Applications

Autor: Jens Kargaard Madsen, Mahsa Esmaeili, Farshad Moradi, Behzad Zeinali

Publikováno v: Zeinali, B, Esmaeili, M, Madsen, J K & Moradi, F 2017, Multilevel SOT-MRAM Cell with a Novel Sensing Scheme for High-Density Memory Applications . in 2017 47th European Solid-State Device Research Conference : ESSDERC 2017 . IEEE, pp. 172-175, European Solid-State Device Research Conference, Leuven, Belgium, 11/09/2017 . https://doi.org/10.1109/ESSDERC.2017.8066619
ESSDERC

This paper presents a multilevel spin-orbit torque magnetic random access memory (SOT-MRAM). The conventional SOT-MRAMs enables a reliable and energy efficient write operation. However, these cells require two access transistors per cell, hence the e

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::da71e6fcb1b7bbe3a77510f5daf6bfba
https://pure.au.dk/portal/da/publications/multilevel-sotmram-cell-with-a-novel-sensing-scheme-for-highdensity-memory-applications(82cd5c07-8dc2-46a2-92b8-3ff7b2165f41).html

8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology

Autor: Farshad Moradi, Mohammad Tohidi, Jens Kargaard Madsen, Behzad Zeinali

Publikováno v: Moradi, F, Tohidi, M, Zeinali, B & Madsen, J K 2015, 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology . in L Claesen, M-T Sanz-Pascual, R Reis & A Sarmiento-Reyes (eds), VLSI-SoC: Internet of Things Foundations : 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6–8, 2014, Revised and Extended Selected Papers . vol. 464, Springer, IFIP AICT-Advances in Information and Communication technology, vol. 464, pp. 95-109, Playa del Carmen, Mexico, 06/10/2014 . https://doi.org/10.1007/978-3-319-25279-7_6
VLSI-SoC: Internet of Things Foundations ISBN: 9783319252780
VLSI-SoC (Selected Papers)

SRAM operation at subthreshold/weak inversion region provides a significant power reduction for digital circuits. SRAM arrays which contribute to a large amount of power consumption for the processors in sub-100 nm technologies, however, cannot benef

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::490545c4990771dc467d81ccfdf52484
https://pure.au.dk/portal/da/publications/8tsram-cell-with-improved-read-and-write-margins-in-65-nm-cmos-technology(dcbcb79b-f935-48ae-968e-df1b7cf4f4fd).html