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pro vyhledávání: '"Barondeau, Olivier"'
Publikováno v:
Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation,
Externí odkaz:
http://arxiv.org/abs/0710.4763
Publikováno v:
Proceedings of the Conference: Design, Automation & Test in Europe; 3/7/2005, Vol. 1, p56-61, 6p