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Novel 20nm hybrid SOI/bulk CMOS technology with 0.183μm/sup 2/ 6T-SRAM cell by immersion lithography
Autor:
null Hou-Yu Chen, null Chang-Yun Chang, null Chien-Chao Huang, null Tang-Xuan Chung, null Sheng-Da Liu, null Jiunn-Ren Hwang, null Yi-Hsuan Liu, null Yu-Jun Chou, null Hong-Jang Wu, null King-Chang Shu, null Chung-Kan Huang, null Jan-Wen You, null Jaw-Jung Shin, null Chun-Kuang Chen, null Chia-Hui Lin, null Ju-Wang Hsu, null Bao-Chin Perng, null Pang-Yen Tsai, null Chi-Chun Chen, null Jyu-Horng Shieh, null Han-Jan Tao, null Shih-Chang Chen, null Tsai-Sheng Gau, null Fu-Liang Yang
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b6438477da572f34e824ad8a96c84a7
https://doi.org/10.1109/.2005.1469194
https://doi.org/10.1109/.2005.1469194
Autor:
Hou-Yu Chen, Chang-Yun Chang, Chien-Chao Huang, Tang-Xuan Chung, Sheng-Da Liu, Jiunn-Ren HwangYi-Hsuan Liu, Yu-Jun Chou, Hong-Jang Wu, King-Chang Shu, Chung-Kan Huang, Jan-Wen You, Jaw-Jung Shin, Chun-Kuang Chen, Chia-Hui Lin, Ju-Wang Hsu, Bao-Chin Perng, Pang-Yen Tsai, Chi-Chun Chen, Jyu-Horng Shieh, Han-Jan Tao
Publikováno v:
2005 Digest of Technical Papers. 2005 Symposium on VLSI Technology; 2005, p16-17, 2p
With the semiconductor market growth, new Integrated Circuit designs are pushing the limit of the technology and in some cases, require specific fine-tuning of certain process modules in manufacturing. Thus the communities of design and technology ar
