Zobrazeno 1 - 10
of 38
pro vyhledávání: '"Balaram Sinharoy"'
Autor:
Pradip Bose, William J. Starke, Christian Zoellin, Ramon Bertran, Satish Kumar Sadasivam, Alper Buyuktosunoglu, Silvia M. Müller, Matthias Pflanz, Robert K. Montoye, Michael Normand Goulet, John-David Wellman, Nagu Dhanwada, Dung Q. Nguyen, Marcy E. Byers, José E. Moreira, Balaram Sinharoy, Richard J. Eickemeyer, Christopher Gonzalez, Thompto Brian W, Andreas Wagner, Karthik Swaminathan, Hans M. Jacobson, Nandhini Chandramoorthy, Michael Stephen Floyd, Jeffrey A. Stuecheli, Rahul M. Rao
Publikováno v:
ISCA
We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62595b871aa8e9aa023304b34a4a6607
https://doi.org/10.1109/isca52012.2021.00012
https://doi.org/10.1109/isca52012.2021.00012
Autor:
Joachim Gerhard Clabes, Joshua Friedrich, J. Kahle, William J. Starke, Daniel M. Dreps, Victor Zyuban, James D. Warnock, Robert Alan Cargnoni, S. Weitzel, Scott A. Taylor, Phillip G. Williams, Jose Angel Paredes, Dieter Wendel, J. Pille, Gaurav Mittal, Saiful Islam, G Smith, J. A. Van Norstrand, Balaram Sinharoy, Phillip J. Restle, David A. Hrusecky, Sam Gat-Shang Chu, Ronald Nick Kalla, Jentje Leenstra
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:145-161
This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 56
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9efa8df1eb9cc07c1be4577681cd9147
https://doi.org/10.1109/jssc.2010.2080611
https://doi.org/10.1109/jssc.2010.2080611
Publikováno v:
IEEE Micro. 30:7-15
The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5fa507a3070f0489ffbb3d996f0c1ec0
https://doi.org/10.1109/mm.2010.38
https://doi.org/10.1109/mm.2010.38
Publikováno v:
IBM Journal of Research and Development. 49:505-521
This paper describes the implementation of the IBM POWER5TM chip, a two-way simultaneous multithreaded dual-core chip, and systems based on it. With a key goal of maintaining both binary and structural compatibility with POWER4TM systems, the POWER5
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5924d31ca3c981603c81a3cb7c99fad
https://doi.org/10.1147/rd.494.0505
https://doi.org/10.1147/rd.494.0505
Publikováno v:
IEEE Micro. 24:40-47
IBM introduced Power4-based systems in 2001. The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c0ddd0b8a892ea764a8628f0442d09c
https://doi.org/10.1109/mm.2004.1289290
https://doi.org/10.1109/mm.2004.1289290
Publikováno v:
IBM Journal of Research and Development. 46:5-25
The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form syste
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d0b5f316d99360639828f2a74706e29
https://doi.org/10.1147/rd.461.0005
https://doi.org/10.1147/rd.461.0005
Autor:
Christopher Gonzalez, David Hogenmiller, Ryan Nett, Daniel M. Dreps, Balaram Sinharoy, Zeynep Toprak Deniz, Phillip J. Restle, Joshua Friedrich, Hung Le, Dave Victor, Victor Zyuban, Matt Ziegler, Frank Malgioglio, Ruchir Puri, Gregory Scott Still, David Shan, Jeff Stuechli, Eric Fluhr, William J. Starke, Dieter Wendel
Publikováno v:
ICICDT
POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and today's exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+™, for many workloads. In addition, POWER8 deli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::875e530993b11a58679595fdd90257ec
https://doi.org/10.1109/icicdt.2014.6838618
https://doi.org/10.1109/icicdt.2014.6838618
Autor:
Balaram Sinharoy
Publikováno v:
Scientific Programming, Vol 7, Iss 1, Pp 21-37 (1999)
Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle), processors stall on cache misses fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c312dec62e666fef12fd679283cf9d29
https://doi.org/10.1155/1999/235625
https://doi.org/10.1155/1999/235625
Language, Compilers and Run-time Systems for Scalable Computers contains 20 articles based on presentations given at the third workshop of the same title, and 13 extended abstracts from the poster session. Starting with new developments in classical
Autor:
Balaram Sinharoy
Publikováno v:
The Computer Journal. 40:388-400
Due to the mismatch in the speed of the processor and the speed of the memory subsystem, modern processors spend a significant portion (often more than 50%) of their execution time stalling on cache misses. Processor multithreading is an approach tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e44ba7fddc7ca9c372704d366b5e78a
https://doi.org/10.1093/comjnl/40.6.388
https://doi.org/10.1093/comjnl/40.6.388