A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.

Autor: Fischette, D.M., Loke, A.L.S., Oshima, M.M., Doyle, B.A., Bakalski, R., DeSantis, R.J., Thiruvengadam, A., Wang, C.L., Talbot, G.R., Fang, E.S.

Publikováno v: 2010 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2010, p246-247, 2p