Výsledky vyhledávání - "Baaij, C.P.R."

Digital circuit in CλaSH: functional specifications and type-directed synthesis

Autor: Baaij, C.P.R.

Over the last three decades, the number of transistors used in microchips has increased by three orders of magnitude, from millions to billions. The productivity of the designers, however, lags behind. Managing to implement complex algorithms, while

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::2e2d0cd36931df163690c3bc1b0a97e7
https://research.utwente.nl/en/publications/5d002ac3-a0fb-4ac0-b344-801f8d8475d8

Zobrazit plný text záznamu

Using Rewriting to Synthesize Functional Languages to Digital Circuits

Autor: Baaij, C.P.R., Kuper, Jan, McCarthy, Jay

Publikováno v: Lecture Notes in Computer Science ISBN: 9783642453397
Trends in Functional Programming
14th International Symposium Trends in Functional Programming, TFP 2013, 17-33
STARTPAGE=17;ENDPAGE=33;TITLE=14th International Symposium Trends in Functional Programming, TFP 2013

A straightforward synthesis from functional languages to digital circuits transforms variables to wires. The types of these variables determine the bit-width of the wires. Assigning a bit-width to polymorphic and function-type variables within this d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::92285c6198d11ef7e142791998c05f2f
https://doi.org/10.1007/978-3-642-45340-3_2

Zobrazit plný text záznamu

A two step hardware design method using CλaSH

Autor: Wester, Rinse, Baaij, C.P.R., Kuper, Jan

Publikováno v: 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, 181-188
STARTPAGE=181;ENDPAGE=188;TITLE=22nd International Conference on Field Programmable Logic and Applications, FPL 2012

In order to effectively utilize the growing number of resources available on FPGAs, higher level abstraction mechanisms are needed to deal with increasing complexity resulting from large designs. Functional hardware description languages, like the C�

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::eef49b81262fddfed704b29d0c008f02
https://research.utwente.nl/en/publications/096a8947-8709-4803-8190-8cd0c2b5f9c8

Zobrazit plný text záznamu

Architecture Specifications in CλaSH

Autor: Kuper, Jan, Baaij, C.P.R., Kooijman, Matthijs, Gerards, Marco Egbertus Theodorus, Kaźmierski, T.J., Morawiec, A.

Publikováno v: System Specification and Design Languages, 191-206
STARTPAGE=191;ENDPAGE=206;TITLE=System Specification and Design Languages
Lecture Notes in Electrical Engineering ISBN: 9781461414261

This paper introduces CλaSH, a novel hardware specification environment, by discussing several non-trivial examples. CλaSH is based on the functional language Haskell, and exploits many of its powerful abstraction mechanisms such as higher order fu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::198a4284c2f9299c6a91ca1a86cbf794
https://research.utwente.nl/en/publications/e9522dd8-a8e7-463e-b7be-645fbabd0466

Zobrazit plný text záznamu

Higher-Order Abstraction in Hardware Descriptions with CλaSH

Autor: Gerards, Marco Egbertus Theodorus, Baaij, C.P.R., Kuper, Jan, Kooijman, Matthijs, Kitsos, P.

Publikováno v: Proceedings of the 14th EUROMICRO Conference on Digital System Design, DSD 2011, 495-502
STARTPAGE=495;ENDPAGE=502;TITLE=Proceedings of the 14th EUROMICRO Conference on Digital System Design, DSD 2011
DSD

Synchronous hardware can be straight forwardly modelled as a function from input and (current) state to an updated state and output. The C?aSH compiler can translate such a transition function, described in a functional language, to synthesisable VHD

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f5824ca2f8eaab008c74c3e953431a88
https://research.utwente.nl/en/publications/f5d1f153-cf21-4bb2-9a86-90febfd29fc6

Zobrazit plný text záznamu

A mathematical approach towards hardware design

Autor: Smit, Gerardus Johannes Maria, Kuper, Jan, Baaij, C.P.R., Athanas, P.M., Becker, J., Teich, J., Verbauwhede, I.

Publikováno v: Dagstuhl Seminar on Dynamically Reconfigurable Architectures

Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstracti

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::b65ee019131fc06f814e999477319d6a
https://research.utwente.nl/en/publications/2876e83f-9200-4aa1-a0ca-d4bf7e254390

Zobrazit plný text záznamu

Comparing CλaSH and VHDL by implementing a dataflow processor

Autor: Niedermeier, A., Wester, Rinse, Baaij, C.P.R., Kuper, Jan, Smit, Gerardus Johannes Maria

Publikováno v: Proceedings of the Workshop on PROGram for Research on Embedded Systems and Software (PROGRESS 2010), 216-221
STARTPAGE=216;ENDPAGE=221;TITLE=Proceedings of the Workshop on PROGram for Research on Embedded Systems and Software (PROGRESS 2010)

As embedded systems are becoming increasingly complex, the design process and verification have become very time-consuming. Additionally, specifying hardware manually in a low-level hardware description language like VHDL is usually an error-prone ta

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::ba777edbd88df52e1a5bcd3725cdfcf9
https://research.utwente.nl/en/publications/comparing-cash-and-vhdl-by-implementing-a-dataflow-processor(5ecc1e5c-8c76-44a9-bf1f-f0c60033d5fa).html

Zobrazit plný text záznamu

Designing a dataflow processor using CλaSH

Autor: Niedermeier, A., Wester, Rinse, Rovers, K.C., Baaij, C.P.R., Kuper, Jan, Smit, Gerardus Johannes Maria

Publikováno v: 28th Norchip Conference, NORCHIP 2010

In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to transl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::41142652b48e3b29d57961ac4bd3b00d
https://research.utwente.nl/en/publications/25caba8a-2fd0-4689-adeb-a1d937fc3a40

Zobrazit plný text záznamu

Exercises in architecture specification using CλaSH

Autor: Kuper, Jan, Baaij, C.P.R., Kooijman, Matthijs, Gerards, Marco Egbertus Theodorus

Publikováno v: Proceedings of Forum on Specification and Design Languages, FDL 2010, 178-183
STARTPAGE=178;ENDPAGE=183;TITLE=Proceedings of Forum on Specification and Design Languages, FDL 2010

This paper introduces the hardware specification system ClaSH by elaborating on a few non-trivial examples. ClaSH is a compiling system that translates a subset of Haskell into synthesizable VHDL by a rewriting technique. This subset of Haskell inclu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::b65e335a2270b353d1f9b466edeb7b7e
https://research.utwente.nl/en/publications/008530b4-9407-41c5-8857-886915864164

Zobrazit plný text záznamu

Hiding State in CλaSH Hardware Descriptions

Autor: Gerards, Marco Egbertus Theodorus, Baaij, C.P.R., Kuper, Jan, Kooijman, Matthijs

Publikováno v: Preproceedings of the 22nd Symposium on Implementation and Application of Functional Languages (IFL 2010), 107-119
STARTPAGE=107;ENDPAGE=119;TITLE=Preproceedings of the 22nd Symposium on Implementation and Application of Functional Languages (IFL 2010)

Synchronous hardware can be modelled as a mapping from input and state to output and a new state, such mappings are referred to as transition functions. It is natural to use a functional language to implement transition functions. The CaSH compiler i

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::79dbbb30afa597bc396040067e699658
https://research.utwente.nl/en/publications/hiding-state-in-cash-hardware-descriptions(d59ee774-bb62-496f-b43e-57e2533f2ddc).html

Zobrazit plný text záznamu

Vyhledávací nástroje:

Upřesnit hledání