Výsledky vyhledávání - "BACIVAROV, I."

Akademický článek

Horizontal Scaling Implementation with Container Orchestrator. Reliability Analysis during Stress and Performance Testing

Autor: DINCA, A.-M., AXINTE, S.-D., BACIVAROV, I., PETRICA, G.

Publikováno v: Advances in Electrical and Computer Engineering, Vol 24, Iss 3, Pp 23-32 (2024)

Software platforms’ infrastructure encompasses the collection of physical resources used concomitantly for user interactions, computational or persistence operations. Virtualization facilitates dynamic allocation of resources to a platform, while

Externí odkaz: https://doaj.org/article/e2be34f30b9b45698b41fd9181527e32

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Dissertation/ Thesis

Evaluation des performances pour les systèmes embarqués hétérogènes, multiprocesseur monopuces

Autor: Bacivarov, I.

Les systèmes embarqués multiprocesseur monopuces (Multi-Processor System-on-Chip, MPSoC) visent l'intégration des sous-systèmes variés, matériels et logiciels, sur une seule puce. Ainsi, l'hétérogénéité et les contraintes imposées pour la

Externí odkaz: http://tel.archives-ouvertes.fr/tel-00086762
http://tel.archives-ouvertes.fr/docs/00/08/67/62/PDF/peh_233.pdf

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Total quality management: a similation-based approach

Autor: Wiele, A, Tcaciuc, S, Bacivarov, I, Balme, L, Goncalves, A, Bacivarov, I., Balme, L., Goncalves, A.

Publikováno v: Quality Management, Assurance and Education; European Dimensions, 44-57
STARTPAGE=44;ENDPAGE=57;TITLE=Quality Management, Assurance and Education; European Dimensions

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=narcis______::839a438781fe1446ac406eaa8244ddd1
https://pure.eur.nl/en/publications/93915326-ccdf-4cc5-ae88-e743a04fbe74

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Performance evaluation for heterogeneous MPSoC design

Autor: Bacivarov, I.

Publikováno v: Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble-INPG, 2006. Français

Multi-processor system-on-chip (MPSoC) is a concept that aims at integrating multiple subsystems on a single chip. Systems that put together complex HW and SW subsystems are difficult to analyze and even harder to optimize. Performance evaluation is

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::25644ebfa05c47e2d78f7d971a34ef66
https://tel.archives-ouvertes.fr/tel-00086762/document

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Performance evaluation methods for MPSoC Design

Autor: Jerraya, A.A., Bacivarov, I.

Publikováno v: EDA for IC System Design, Verification, and Testing
EDA for IC System Design, Verification, and Testing, CRC Press, Chapter 6, 2006, Series: Electronic Design Automation for Integrated Circuits Hdbk

ISBN: 0849379237; Multi-processor systems-on-chip (MPSoCs) require the integration of heterogeneous components (e.g., micro-processors, DSP, ASIC, memories, buses, etc.) on a single chip. The design of MPSoC architectures requires the exploration of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::4d704b128c5359f340ee3ebbf042415d
https://hal.archives-ouvertes.fr/hal-00105210

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A fast and accurate validation technique for operating system in multi-processor system-on-chip design

Autor: Bacivarov, I., Jerraya, A.A., Yoo, S.

Publikováno v: Proceedings-of-the-SPIE-The-International-Society-for-Optical-Engineering
Proceedings-of-the-SPIE-The-International-Society-for-Optical-Engineering.
Proceedings-of-the-SPIE-The-International-Society-for-Optical-Engineering, SPIE-Int. Soc. Opt. Eng, 2004, 5227(1):, pp.342-8. ⟨10.1117/12.520078⟩

Modern electronic system design is based on integrating heterogeneous components ( mu P, DSP, ASIC, memories, buses, MEMS, MOEMS, etc.) on a single chip. These highly integrated systems are commonly known as System-on-Chip (SoC). System validation by

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::e0f6c18c6430b199a5653644670b164a
https://hal.archives-ouvertes.fr/hal-00008041

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Building fast and accurate SW simulation models based on hardware abstraction layer and simulation environment abstraction layer

Autor: Yoo, S., Bacivarov, I., Bouchhima, A., Paviot, Y., Jerraya, A.A.

Publikováno v: Proceedings-Design,-Automation-and-Test-in-Europe-Conference-and-Exhibition.

As a fast and accurate SW simulation model, we present a model called fast timed SW model. The model enables fast simulation by native execution of application SW and OS. It gives simulation accuracy by timed SW and HW simulation. When building fast

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::b1746a30cea84a531e3afdc72ff8a253
https://hal.archives-ouvertes.fr/hal-00008053

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Timed HW-SW cosimulation using native execution of OS and application SW

Autor: Bacivarov, I., Yoo, S., Jerraya, A.A.

Publikováno v: Proceedings-Seventh-IEEE-International-High-Level-Design-Validation-and-Test-Workshop

We present a method of timed HW-SW cosimulation which uses native execution of OS and application SW. The method presents fast and accurate cosimulation. Since the OS and application SW are executed natively on the simulation host, it gives faster si

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::fcd4d9be4a8bc27bc44a2a421cae4617
https://hal.archives-ouvertes.fr/hal-00008057

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