Zobrazeno 1 - 10
of 35
pro vyhledávání: '"B.P. Hu"'
Autor:
C.-J.R. Shi, B.P. Hu
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:883-892
Even for a single circuit, it has become increasingly time consuming to simulate at the SPICE level. However, the situation is getting worse when it comes to simulating thousands of such circuits, where often one circuit is closely related to another
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::21e1976a972ca7867ed38632f2c7250b
https://doi.org/10.1109/tcad.2008.917593
https://doi.org/10.1109/tcad.2008.917593
Publikováno v:
ICCD
A 1024-bit, 1/2-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18 mum fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The 3D-IC d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c49ac3b5faab0db525c16bb5536017d1
https://doi.org/10.1109/iccd.2007.4601900
https://doi.org/10.1109/iccd.2007.4601900
Publikováno v:
ASP-DAC
A 1024-bit, 1/2 -rate fully parallel low density parity check (LDPC) code decoder has been designed and implemented using a 3D 0.18/spl mu/m fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D decoder
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e1cb0146900ec1dd7ed49ae0026092b
https://doi.org/10.1109/aspdac.2006.1594652
https://doi.org/10.1109/aspdac.2006.1594652
Publikováno v:
Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation.
Symbolic model order reduction (SMOR) is the problem of reducing a large circuit that contains symbolic circuit parameters to smaller low order models at its ports. Several methods, including symbol isolation, single frequency point reduction, and mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::834070fb23666c65d30f9f63141949f1
https://doi.org/10.1109/bmas.2003.1249854
https://doi.org/10.1109/bmas.2003.1249854
Publikováno v:
CICC
This paper introduces MCAST: a model compiler - based on abstract syntax trees - that reads compact device models described in high-level languages VHDL-AMS/Verilog-AMS and automatically generates the simulator device code in C that can be directly l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66e8a189dacb516eee350fba80826dde
https://doi.org/10.1109/cicc.2003.1249397
https://doi.org/10.1109/cicc.2003.1249397
Publikováno v:
IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..
VHDL-AMS and Verilog-AMS are behavioral languages extended from widely used VHDL/Verilog for analog and mixed-signal applications. By describing models in the behavioral language VHDL-AMS/Verilog-AMS and then compiling them with a model compiler such
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c0adeb4bbc9b7c7dd44d78a22fd4d50
https://doi.org/10.1109/soc.2003.1241523
https://doi.org/10.1109/soc.2003.1241523
Akademický článek
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Publikováno v:
Animal, Vol 6, Iss 6, Pp 941-951 (2012)
Previous studies in prepubertal heifers suggest that the magnitude of reduction in mammary parenchymal growth in response to ovariectomy varies with the age at which surgery is performed. We hypothesized that ovarian secretions are essential for init
Externí odkaz:
https://doaj.org/article/50874387abfc4e99bb2071549525b982
Akademický článek
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