Zobrazeno 1 - 10
of 12
pro vyhledávání: '"B.J. Benschneider"'
Autor:
B.J. Benschneider, D.W. Bailey
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1627-1633
The clocking methodology for the 600 MHz Alpha microprocessor allows increased performance goals to be met through multi-level buffering. In addition power savings are realized through reduced metal usage and conditional clocks. Two distinct analysis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d236fd98d3b11162cca6df5bd017dfb2
https://doi.org/10.1109/4.726547
https://doi.org/10.1109/4.726547
Autor:
Elizabeth M. Cooper, William J. Bowhill, B.J. Benschneider, V.K. Maheshwari, M.N. Gavrielov, J.D. Pickholtz, Paul E. Gronowski, Sridhar Samudrala, V. Peng
Publikováno v:
IEEE International Solid-State Circuits Conference.
A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e02992ff7681e16ec7ad38bbda92832
https://doi.org/10.1109/isscc.1989.48229
https://doi.org/10.1109/isscc.1989.48229
Autor:
V. Peng, Sridhar Samudrala, Elizabeth M. Cooper, W.V. Herrick, A Fisher, D.E. Sanders, Randy L. Allmon, W.H. Durdan, Paul E. Gronowski, D. Kravitz, P.J. Starvaski, L. Madden, R.C. Marcello, V.K. Maheshwari, G.G. Mills, J.F. Brown, William J. Bowhill, W.R. Wheeler, M. Mittal, W.J. Grundmann, M.N. Gavrielov, J.D. Pickholtz, B.J. Benschneider, R.L. Stamm
Publikováno v:
IEEE International Solid-State Circuits Conference.
A four-chip custom VLSI implementation of a 32-b computer comprised of a CPU, a secondary cache controller, a floating-point accelerator, and a clock generator is described. It operates at a cycle time of 28 ns and is compatible with an existing comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29c00422818686241ddc04191e4d092c
https://doi.org/10.1109/isscc.1989.48187
https://doi.org/10.1109/isscc.1989.48187
Autor:
M.K. Gowan, J.B. Keller, B.J. Benschneider, Harry R. Fair, M.J. Smith, V. Peng, Kathryn Wilcox, Sharon M. Britton, R. Allmon, C.L. Houghton, Donald A. Priore, B. Gieseke, D.L. Leibholz, Jim Farrell, M.D. Matson, J.D. Clouser, T.H. Lee, R.J. Matthew, S.C. Lowell, M.D. Quinn, D.W. Bailey
Publikováno v:
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
A six-issue, four-fetch, out-of-order execution, 6OOMHz Alpha microprocessor achieves an estimated 40SpecInt95, 60SpecFP95 and 1800MB/s on McCalpin Stream. The 16.7x18.8mm2 die contains 15.2M transistors and dissipates an estimated 72W. It is in 2.0V
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::843d4addfb8ecbbcb45a0f0d1b8b0522
https://doi.org/10.1109/isscc.1997.585323
https://doi.org/10.1109/isscc.1997.585323
Autor:
B.J. Benschneider, null Sungho Park, R. Allmon, W. Anderson, M. Arneborn, null Jangho Cho, null Changjun Ghoi, J. Clouser, null Sangok Han, R. Hokinson, null Gyoocheol Hwang, null Daesuk Jung, null Jaeyoon Kim, J. Krause, J. Kwack, S. Meier, null Yongsik Seok, S. Thierauf, C. Zhou
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
A 6-way out-of-order issue custom VLSI implementation of the Alpha architecture runs at >1 GHz. The 13.1/spl times/14.7 mm/sup 2/ die contains 15.2 M transistors and utilizes 0.18 /spl mu/m CMOS which includes 7 aluminum interconnect layers and flip-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a618bb3ad5e565616bebf3779a57134b
https://doi.org/10.1109/isscc.2000.839702
https://doi.org/10.1109/isscc.2000.839702
Autor:
L. Hudepohl, R. Allmon, S. Samudrala, D.E. Dever, J. Farrell, R.C. Marcello, D.E. Sanders, J. Lundberg, N. Fitzgerald, M. Richesson, J. Grodstein, L. Chao, B.J. Benschneider, J.D. Pickholtz, M. Callander, Soha Hassoun, D. Kravitz, S. Marino, R.P. Preston
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
The system, process, and design implications of converting a microprocessor chip set originally implemented in a 5-V, 1.5- mu m (drawn) CMOS process to one implemented in a 3.3-V, 1.0- mu m (drawn) CMOS process are described. The chip set is 75% fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fa689077638e7c2fea5866d175603aa
https://doi.org/10.1109/isscc.1990.110123
https://doi.org/10.1109/isscc.1990.110123
Autor:
V. Peng, W.J. Bowhill, V.K. Maheshwari, S. Samudrala, P.E. Gronowski, E.M. Copper, B.J. Benschneider, M.N. Gavrielov, J.D. Pickholtz
Publikováno v:
IEEE Journal of Solid-State Circuits. 24:1317-1323
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except do
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae6b8abdcaf9a0bc6464df57fb918bc0
https://doi.org/10.1109/jssc.1989.572606
https://doi.org/10.1109/jssc.1989.572606
Akademický článek
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Akademický článek
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Conference
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