Zobrazeno 1 - 10
of 30
pro vyhledávání: '"B. van Schravendijk"'
Autor:
T. Nogami, S. Nguyen, H. Huang, N. Lanzillo, H. Shobha, J. Li, B. Peethela, A. Parbatani, B. van Schravendijk, B. Varadarajan, I. Narkeviciute, E. Srinivasan, K. Sharma, R. Knarr, S. Schmitz, V. Ramanan, D. Edelstein
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::89a86e1c7f8fdaa73dad0d9243815490
https://doi.org/10.1109/iedm19574.2021.9720525
https://doi.org/10.1109/iedm19574.2021.9720525
Autor:
P. Ruault, Gong Bo, O. Hinsinger, B. van Schravendijk, D. Winandy, C. Fenouillet-Beranger, D. Galpin, D. Vo-Thanh, S. Lagrasta, Romain Duru, Remi Beneyton, C. Gaumer, J. Mazurier, S. Chhun, N. Chauvet, Bhadri N. Varadarajan, D. Barge, P. Meijer, N. Sun, Daniel Benoit
Publikováno v:
2015 IEEE International Electron Devices Meeting (IEDM)
For the first time, the interest of a new SiCO low-k spacer material deposited at 400°C is evaluated in the perspective of a 3D VLSI integration. The benefits of SiCO low-k (4.5 vs 7 for SiN) value is preserved throughout the whole integration and t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::55b982f281a226468041de5b5459d450
https://doi.org/10.1109/iedm.2015.7409656
https://doi.org/10.1109/iedm.2015.7409656
Autor:
J.C. Dupuy, G. Bryce, Nicolas Gaillard, S. Chhun, J. Vitiello, V. Girault, M. Hopstaken, J. Guillan, Joaquim Torres, L.G. Gosset, B. Van Schravendijk, J. Michelon, Pascal Bancken, S. Courtas, R. Gras, Marc Juhel, L. Pinzelli, C. Debauche
Publikováno v:
Microelectronic Engineering. 83:2094-2100
Self-aligned barriers are widely investigated either in replacement of dielectric liners to decrease the total interconnect k value or as a treatment prior standard dielectric barrier deposition to improve reliability performances. In this paper, a t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a69f8a8c59131b6a249c8aad8379dfdd
https://doi.org/10.1016/j.mee.2006.09.013
https://doi.org/10.1016/j.mee.2006.09.013
Autor:
B. van Schravendijk, M. Sekine, Kaushik Chattopadhyay, T. Ide, Y. Ajima, Yu Yongsik, Y. Kakuhara, E. Apen, K. Ueno, Tatsuya Usami, Noriaki Oda, T. Maruyama
Publikováno v:
2006 International Interconnect Technology Conference.
A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) has been developed for 65nm node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::699dd39b6fa15485acc347d46bf7b944
https://doi.org/10.1109/iitc.2006.1648665
https://doi.org/10.1109/iitc.2006.1648665
Publikováno v:
Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).
As aluminum reactive ion etch (RIE) technology extends to sub-0.20 /spl mu/m technology, a void-free back-end-of-line (BEOL) gap-fill process is one of the major challenges for interconnects. When a stitched word line architecture is employed, the fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ebce1e4239b99041522cd8df40673984
https://doi.org/10.1109/iitc.1999.787106
https://doi.org/10.1109/iitc.1999.787106
Publikováno v:
Proceedings of the Bipolar Circuits and Technology Meeting.
It is shown that a localized collectivity implant can be used to improve the device performance as well as to increase the uniformity of device characteristics over the wafer of single polysilicon bipolar transistors. These advantages, which do not r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f58bc81c2dc5ee599bab8f5d4fa47a24
https://doi.org/10.1109/bipol.1989.69482
https://doi.org/10.1109/bipol.1989.69482
Publikováno v:
Proceedings of the Bipolar Circuits and Technology Meeting.
A single-polysilicon-layer advanced super-high-speed (HS4+) BiCMOS technology which offers 1- mu m NMOS and PMOS devices, 13-GHz bipolar npn transistors, lateral pnps, Schottky diodes, polysilicon resistors, lateral fuses, and three layers of Al/Cu i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6633811cd6ab126f72f5dff745f120a5
https://doi.org/10.1109/bipol.1989.69487
https://doi.org/10.1109/bipol.1989.69487
Autor:
B. van Schravendijk, P. Maillot
Publikováno v:
Proceedings of the Bipolar Circuits and Technology Meeting.
Some of the limitations and consequences of scaling the polysilicon-emitter/implanted-base structure in advanced bipolar transistors are explored. It is found that ion implantation for the base below 10 keV is unattractive. It is also found that the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::846750bf8f0b03fb1268a7b3c15dcf76
https://doi.org/10.1109/bipol.1989.69464
https://doi.org/10.1109/bipol.1989.69464
Publikováno v:
Proceedings of the 1988 Bipolar Circuits and Technology Meeting.
The method of double-diffused emitter-base formation is characterized. It is shown to be a viable technique for the fabrication of advanced bipolar transistors. The use of amorphous instead of polycrystalline silicon as the emitter contact material r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f83ba8ad92f8f25c5216f3b92bc8b876
https://doi.org/10.1109/bipol.1988.51064
https://doi.org/10.1109/bipol.1988.51064
Publikováno v:
Proceedings on Bipolar Circuits and Technology Meeting.
A novel technique for well design for advanced BiCMOS is demonstrated. By optimization of the well doping the QUBiC2 process achieves 17-GHz bipolar transistors and 0.5- mu m L/sub eff/ CMOS. This technique has been demonstrated to form updiffused re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e458819ee322655f406f69c1772ac01
https://doi.org/10.1109/bipol.1990.171152
https://doi.org/10.1109/bipol.1990.171152